Abstract: Face is a non-intrusive strong biometrics for
identification of original and dummy facial by different artificial
means. Face recognition is extremely important in the contexts of
computer vision, psychology, surveillance, pattern recognition,
neural network, content based video processing. The availability of a
widespread face database is crucial to test the performance of these
face recognition algorithms. The openly available face databases
include face images with a wide range of poses, illumination, gestures
and face occlusions but there is no dummy face database accessible in
public domain. This paper presents a face detection algorithm based on
the image segmentation in terms of distance from a fixed point and
template matching methods. This proposed work is having the most
appropriate number of nodal points resulting in most appropriate
outcomes in terms of face recognition and detection. The time taken to
identify and extract distinctive facial features is improved in the range
of 90 to 110 sec. with the increment of efficiency by 3%.
Abstract: In this paper, firstly, we present the mathematical modeling of finite impulse response (FIR) filter and Cascaded Integrator Comb (CIC) filter for sampling rate reduction and then an extension of Canonical signed digit (CSD) based efficient structure is presented in framework using hybrid signed digit (HSD) arithmetic. CSD representation imposed a restriction that two non-zero CSD coefficient bits cannot acquire adjacent bit positions and therefore, represented structure is not economical in terms of speed, area and power consumption. The HSD based structure gives optimum performance in terms of area and speed with 37.02% passband droop compensation.
Abstract: In many communication and signal processing
systems, it is highly desirable to implement an efficient narrow-band
filter that decimate or interpolate the incoming signals. This paper
presents hardware efficient compensated CIC filter over a narrow
band frequency that increases the speed of down sampling by using
multiplierless decimation filters with polyphase FIR filter structure.
The proposed work analyzed the performance of compensated CIC
filter on the bases of the improvement of frequency response with
reduced hardware complexity in terms of no. of adders and
multipliers and produces the filtered results without any alterations.
CIC compensator filter demonstrated that by using compensation
with CIC filter improve the frequency response in passed of interest
26.57% with the reduction in hardware complexity 12.25%
multiplications per input sample (MPIS) and 23.4% additions per
input sample (APIS) w.r.t. FIR filter respectively.
Abstract: Unwanted side effects because of spectral aliasing and spectral imaging during signal processing would be the major concern over the sampling rate alteration. Multirate-multistage implementation of digital filter could come about a large computational saving than single rate filter suitable for sample rate conversion. This implementation can further improve through high-level architectural transformation in circuit level. Reallocating registers and relocating flip-flops across logic gates through retiming certainly a prominent sequential transformation technology, that optimize hardware circuits to achieve faster clocking speed without affecting the functionality. In this paper, we proposed an efficient compensated cascade Integrator comb (CIC) decimation filter structure that analyze the consequence of filter order variation which has a retimed FIR filter being compensator while using the cutset retiming technique and achieved an improvement in the passband droop by 14% to 39%, in computation time by 38.04%, 25.78%, 12.21%, 6.69% and 4.44% and reduction in path delay by 62.27%, 72%, 86.63%, 91.56% and 94.42% of 3, 6, 8, 12 and 24 order filter respectively than the non-retimed CIC compensation filter.
Abstract: Any digital processing performed on a signal with larger nyquist interval requires more computation than signal processing performed on smaller nyquist interval. The sampling rate alteration generates the unwanted effects in the system such as spectral aliasing and spectral imaging during signal processing. Multirate-multistage implementation of digital filter can result a significant computational saving than single rate filter designed for sample rate conversion. In this paper, we presented an efficient cascaded integrator comb (CIC) decimation filter that perform fast down sampling using signed digit adder algorithm with compensated frequency droop that arises due to aliasing effect during the decimation process. This proposed compensated CIC decimation filter structure with a hybrid signed digit (HSD) fast adder provide an improved performance in terms of down sampling speed by 65.15% than ripple carry adder (RCA) and reduced area and power by 57.5% and 0.01 % than signed digit (SD) adder algorithms respectively.