Abstract: This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.
Abstract: Internet Protocol version 4 (IPv4) address is decreasing and a rapid transition method to the next generation IP address (IPv6) should be established. This study aims to evaluate and select the best performance of the IPv6 address network transitionmechanisms, such as IPv4/IPv6 dual stack, transport Relay Translation (TRT) and Reverse Proxy with additional features. It is also aim to prove that faster access can be done while ensuring optimal usage of available resources used during the test and actual implementation. This study used two test methods such asInternet Control Message Protocol (ICMP)ping and ApacheBenchmark (AB) methodsto evaluate the performance.Performance metrics for this study include aspects ofaverageaccessin one second,time takenfor singleaccess,thedata transfer speed and the costof additional requirements.Reverse Proxy with Caching featureis the most efficientmechanism because of it simpler configurationandthe best performerfrom the test conducted.