Designing of Full Adder Using Low Power Techniques

This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.

• Shashank Gautam

• Low Power
• MT CMOS
• Galeor
• Lector
• Power Gating
• Dual Stack
• Full Adder.

[1] Johnson M, Somasekhar D, Chiou L-Y, et al. Leakage control with
efficient use of transistor stacks in single threshold CMOS. IEEE Trans.
Very Large Scale Integration. (VLSI) Syst. 1–5 Feb 2002; 10(1).
[2] Kang S. Accurate simulation of power dissipation in VLSI circuits.
IEEE Journal of Solid-State Circuits. 1986; 889–91p
[3] Hyo-Sig Won, et al. An MTCMOS design methodology and its
application to mobile computing. Intl. Symp. on Low Power Electronics
and Design. 2003; 110–15p
[4] Saxena Chhavi, Pattanaik Manisha, Tiwari RK. Enhanced power gating
schemes for low leakage low ground bounce noise in deep submicron
circuits. IEEE. 2012. [5] Roy K, Mukhopadhyay S, Mahmoodi-Meimand H. Leakage current
mechanisms and leakage reduction techniques in deep-sub-micrometer
CMOS circuits. In Proc. IEEE Feb. 2003; 91: 305–27p
[6] Park JC, Mooney III VJ, Pfeiffenberger P. Sleepy stack reduction of
leakage power. Proceeding of International Workshop on Power and
Timing Modeling, Optimization and Simulation. September 2004; 148–
58p
[7] Balabanian N, Carlson B. Digital Logic Design Principles. John Wily &
Sons, Inc. 2001.
[8] Zhao P, Darwish T, Bayoumi M. High-performance and low power
conditional discharge flip-flop. IEEE Trans Very Large Scale Integration
(VLSI) Syst. May 2004; 12(5): 477–84p.
[9] Seta K, Hara H, Kuroda T, et al. 50% active-power saving without speed
degradation using standby power reduction (SPR) circuit. In Proceedings
of the IEEE International Solid State Circuits Conference. 1995
[10] Hanchate N, Ranganathan N. LECTOR: A technique for leakage
reduction in CMOS circuits. IEEE Transactions on VLSI Systems Feb.,
2004; 12: 196–205p.
[11] Gautam Shashank. Low Power and High Speed Techniques for
Sequential Circuits. Journal of Power Electronics & Power Systems
(2014) 41-45p.