Abstract: In present era, development of digital circuits, signal processors and other integrated circuits, magnitude comparators are challenged by large area and more power consumption. Comparator is most basic circuit that performs comparison. This paper presents a technique to design a two bit comparator which consumes less area and power. DSCH and MICROWIND version 3 are used to design the schematic and design the layout of the schematic, observe the performance parameters at different nanometer technologies respectively.
Abstract: This paper proposes techniques like MT CMOS,
POWER GATING, DUAL STACK, GALEOR and LECTOR to
reduce the leakage power. A Full Adder has been designed using
these techniques and power dissipation is calculated and is compared
with general CMOS logic of Full Adder.
Simulation results show the validity of the proposed techniques is
effective to save power dissipation and to increase the speed of
operation of the circuits to a large extent.