Abstract: In this paper, a novel Linear Feedback Shift Register
(LFSR) with Look Ahead Clock Gating (LACG) technique is
presented to reduce the power consumption in modern processors
and System-on-Chip. Clock gating is a predominant technique used
to reduce unwanted switching of clock signals. Several clock gating
techniques to reduce the dynamic power have been developed, of
which LACG is predominant. LACG computes the clock enabling
signals of each flip-flop (FF) one cycle ahead of time, based on the
present cycle data of the flip-flops on which it depends. It overcomes
the timing problems in the existing clock gating methods like datadriven
clock gating and Auto-Gated flip-flops (AGFF) by allotting a
full clock cycle for the determination of the clock enabling signals.
Further to reduce the power consumption in LACG technique, FFs
can be grouped so that they share a common clock enabling signal.
Simulation results show that the novel grouped LFSR with LACG
achieves 15.03% power savings than conventional LFSR with LACG
and 44.87% than data-driven clock gating.
Abstract: An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.