Abstract: Expression data analysis is based mostly on the
statistical approaches that are indispensable for the study of
biological systems. Large amounts of multidimensional data resulting
from the high-throughput technologies are not completely served by
biostatistical techniques and are usually complemented with visual,
knowledge discovery and other computational tools. In many cases,
in biological systems we only speculate on the processes that are
causing the changes, and it is the visual explorative analysis of data
during which a hypothesis is formed. We would like to show the
usability of multidimensional visualization tools and promote their
use in life sciences. We survey and show some of the
multidimensional visualization tools in the process of data
exploration, such as parallel coordinates and radviz and we extend
them by combining them with the self-organizing map algorithm. We
use a time course data set of transitional cell carcinoma of the bladder
in our examples. Analysis of data with these tools has the potential to
uncover additional relationships and non-trivial structures.
Abstract: Nuclear matrix protein 22 (NMP22) is a FDA approved
biomarker for bladder cancer. The objective of this study is to develop
a simple NMP22 immumosensor (NMP22-IMS) for accurate
measurement of NMP22. The NMP22-IMS was constructed with
NMP22 antibody immobilized on screen-printed carbon electrodes.
The construction procedures and antibody immobilization are simple.
Results showed that the NMP22-IMS has an excellent (r2³0.95)
response range (20 – 100 ng/mL). In conclusion, a simple and reliable
NMP22-IMS was developed, capable of precisely determining urine
NMP22 level.
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: This paper focuses on robust design and optimization
of industrial production wastes. Past literatures were reviewed to case
study Clamason Industries Limited (CIL) - a leading ladder-tops
manufacturer. A painstaking study of the firm-s practices at the shop
floor revealed that Over-production, Waiting time, Excess inventory,
and Defects are the major wastes that are impeding their progress and
profitability. Design expert8 software was used to apply Taguchi
robust design and response surface methodology in order to model,
analyse and optimise the wastes cost in CIL. Waiting time and overproduction
rank first and second in contributing to the costs of wastes
in CIL. For minimal wastes cost the control factors of overproduction,
waiting-time, defects and excess-inventory must be set at
0.30, 390.70, 4 and 55.70 respectively for CIL. The optimal value of
cost of wastes for the months studied was 22.3679. Finally, a
recommendation was made that for the company to enhance their
profitability and customer satisfaction, they must adopt the Shingeo
Shingo-s Single Minute Exchange of Dies (SMED), which will
immediately tackle the waste of waiting by drastically reducing their
setup time.
Abstract: For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16×16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
Abstract: In this paper, we present the design and experimental
evaluation of complementary energy path adiabatic logic (CEPAL)
based 1 bit full adder circuit. A simulative investigation on the
proposed full adder has been done using VIRTUOSO SPECTRE
simulator of cadence in 0.18μm UMC technology and its
performance has been compared with the conventional CMOS full
adder circuit. The CEPAL based full adder circuit exhibits the energy
saving of 70% to the conventional CMOS full adder circuit, at 100
MHz frequency and 1.8V operating voltage.
Abstract: with increasing circuits- complexity and demand to
use portable devices, power consumption is one of the most
important parameters these days. Full adders are the basic block of
many circuits. Therefore reducing power consumption in full adders
is very important in low power circuits. One of the most powerconsuming
modules in full adders is XOR/XNOR circuit. This paper
presents two new full adders based on two new logic approaches. The
proposed logic approaches use one XOR or XNOR gate to implement
a full adder cell. Therefore, delay and power will be decreased. Using
two new approaches and two XOR and XNOR gates, two new full
adders have been implemented in this paper. Simulations are carried
out by HSPICE in 0.18μm bulk technology with 1.8V supply voltage.
The results show that the ten-transistors proposed full adder has 12%
less power consumption and is 5% faster in comparison to MB12T
full adder. 9T is more efficient in area and is 24% better than similar
10T full adder in term of power consumption. The main drawback of
the proposed circuits is output threshold loss problem.
Abstract: The proposed multiplexer-based novel 1-bit full
adder cell is schematized by using DSCH2 and its layout is generated
by using microwind VLSI CAD tool. The adder cell layout
interconnect analysis is performed by using BSIM4 layout analyzer.
The adder circuit is compared with other six existing adder circuits
for parametric analysis. The proposed adder cell gives better
performance than the other existing six adder circuits in terms of
power, propagation delay and PDP. The proposed adder circuit is
further analyzed for interconnect analysis, which gives better
performance than other adder circuits in terms of layout thickness,
width and height.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: Distributed Computing Systems are usually considered the most suitable model for practical solutions of many parallel algorithms. In this paper an enhanced distributed system is presented to improve the time complexity of Binary Indexed Trees (BIT). The proposed system uses multi-uniform processors with identical architectures and a specially designed distributed memory system. The analysis of this system has shown that it has reduced the time complexity of the read query to O(Log(Log(N))), and the update query to constant complexity, while the naive solution has a time complexity of O(Log(N)) for both queries. The system was implemented and simulated using VHDL and Verilog Hardware Description Languages, with xilinx ISE 10.1, as the development environment and ModelSim 6.1c, similarly as the simulation tool. The simulation has shown that the overhead resulting by the wiring and communication between the system fragments could be fairly neglected, which makes it applicable to practically reach the maximum speed up offered by the proposed model.
Abstract: Parallel Prefix addition is a technique for improving
the speed of binary addition. Due to continuing integrating intensity
and the growing needs of portable devices, low-power and highperformance
designs are of prime importance. The classical parallel
prefix adder structures presented in the literature over the years
optimize for logic depth, area, fan-out and interconnect count of logic
circuits. In this paper, a new architecture for performing 8-bit, 16-bit
and 32-bit Parallel Prefix addition is proposed. The proposed prefix
adder structures is compared with several classical adders of same
bit width in terms of power, delay and number of computational
nodes. The results reveal that the proposed structures have the least
power delay product when compared with its peer existing Prefix
adder structures. Tanner EDA tool was used for simulating the adder
designs in the TSMC 180 nm and TSMC 130 nm technologies.
Abstract: Finite impulse response (FIR) filters have the advantage of linear phase, guaranteed stability, fewer finite precision errors, and efficient implementation. In contrast, they have a major disadvantage of high order need (more coefficients) than IIR counterpart with comparable performance. The high order demand imposes more hardware requirements, arithmetic operations, area usage, and power consumption when designing and fabricating the filter. Therefore, minimizing or reducing these parameters, is a major goal or target in digital filter design task. This paper presents an algorithm proposed for modifying values and the number of non-zero coefficients used to represent the FIR digital pulse shaping filter response. With this algorithm, the FIR filter frequency and phase response can be represented with a minimum number of non-zero coefficients. Therefore, reducing the arithmetic complexity needed to get the filter output. Consequently, the system characteristic i.e. power consumption, area usage, and processing time are also reduced. The proposed algorithm is more powerful when integrated with multiplierless algorithms such as distributed arithmetic (DA) in designing high order digital FIR filters. Here the DA usage eliminates the need for multipliers when implementing the multiply and accumulate unit (MAC) and the proposed algorithm will reduce the number of adders and addition operations needed through the minimization of the non-zero values coefficients to get the filter output.
Abstract: Trihalomethanes (THMs) were among the first
disinfection byproducts to be discovered in chlorinated water. The
substances form during a reaction between chlorine and organic
matter in the water. Trihalomethanes are suspected to have negative
effects on birth such as, low birth weight, intrauterine growth
retardation in term births, as well as gestational age and preterm
delivery. There are also some evidences showing these by-products to
be mutagenic and carcinogenic, the greatest amount of evidence being
related to the bladder cancer. However, there exist inconsistencies
regarding such effects of THMs as different studies have provided
different results in this regard. The aim of the present study is to
provide a review of the related researches about the above mentioned
health effects of THMs.
Abstract: In this study, inhibition of Microcystis aeruginosa by
antialgal alleochemical gramine, was studied by analyzing algal
metabolic activity (represented by esterase and total dehydrogenase
activities) and cell ultrastructure (showing morphological and
ultrastructure alterations using transmission electron microscopy and
DNA ladder analysis). After gramine exposure, esterase and total
dehydrogenase activities were increased firstly but decreased later. In
contrast with the controls, the cells exposed to gramine showed
apparent ultrastructure alterations with thylakoids in breakage,
phycobilins in decrease, lipid and cyanophycin granules abundant
firstly but dissolved afterwards, DNA in fragementation. The
occurrence of increase of metabolic activity and specific granules
reflected that the resistance of cellular response to gramine was
initiated. DNA fragementation associated with the increase of
metabolic activity and specific granules hinted that gramine caused M.
aeruginosa cells to initiate some morphotype of programmed cell
death.
Abstract: In this paper, a new reverse converter for the moduli set {2n, 2n–1, 2n–1–1} is presented. We improved a previously introduced conversion algorithm for deriving an efficient hardware design for reverse converter. Hardware architecture of the proposed converter is based on carry-save adders and regular binary adders, without the requirement for modular adders. The presented design is faster than the latest introduced reverse converter for moduli set {2n, 2n–1, 2n–1–1}. Also, it has better performance than the reverse converters for the recently introduced moduli set {2n+1–1, 2n, 2n–1}
Abstract: Image watermarking has proven to be quite an
efficient tool for the purpose of copyright protection and
authentication over the last few years. In this paper, a novel image
watermarking technique in the wavelet domain is suggested and
tested. To achieve more security and robustness, the proposed
techniques relies on using two nested watermarks that are embedded
into the image to be watermarked. A primary watermark in form of a
PN sequence is first embedded into an image (the secondary
watermark) before being embedded into the host image. The
technique is implemented using Daubechies mother wavelets where
an arbitrary embedding factor α is introduced to improve the
invisibility and robustness. The proposed technique has been applied
on several gray scale images where a PSNR of about 60 dB was
achieved.
Abstract: A Positron Emission Tomography (PET) is a radioisotope imaging technique that illustrates the organs and the metabolisms of the human body. This technique is based on the simultaneous detection of 511 keV annihilation photons, annihilated as a result of electrons annihilating positrons that radiate from positron-emitting radioisotopes that enter biological active molecules in the body. This study was conducted on ten patients in an effort to conduct patient-related experimental studies. Dosage monitoring for the bladder, which was the organ that received the highest dose during PET applications, was conducted for 24 hours. Assessment based on measuring urination activities after injecting patients was also a part of this study. The MIRD method was used to conduct dosage calculations for results obtained from experimental studies. Results obtained experimentally and theoretically were assessed comparatively.
Abstract: In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
Abstract: Modular multiplication is the basic operation
in most public key cryptosystems, such as RSA, DSA, ECC,
and DH key exchange. Unfortunately, very large operands
(in order of 1024 or 2048 bits) must be used to provide
sufficient security strength. The use of such big numbers
dramatically slows down the whole cipher system, especially
when running on embedded processors.
So far, customized hardware accelerators - developed on
FPGAs or ASICs - were the best choice for accelerating
modular multiplication in embedded environments. On the
other hand, many algorithms have been developed to speed
up such operations. Examples are the Montgomery modular
multiplication and the interleaved modular multiplication
algorithms. Combining both customized hardware with
an efficient algorithm is expected to provide a much faster
cipher system.
This paper introduces an enhanced architecture for computing
the modular multiplication of two large numbers X
and Y modulo a given modulus M. The proposed design is
compared with three previous architectures depending on
carry save adders and look up tables. Look up tables should
be loaded with a set of pre-computed values. Our proposed
architecture uses the same carry save addition, but replaces
both look up tables and pre-computations with an enhanced
version of sign detection techniques. The proposed architecture
supports higher frequencies than other architectures.
It also has a better overall absolute time for a single operation.
Abstract: The main purpose of the dam is to control the surface
streams and rivers across the country. Dam construction and
formation of river and big water reservoirs and resources happen in
the glen is a big incident which would change its surrounding area
considerably. In fact, constructing a dam the glen width is close and
fishes don't migrate from upstream to downstream and ultimately it
would led to their death. To resolve this, it seems necessity to create a
passage for fishes during the construction of dam. It is provided
establishing a set of stepped pools overlooking each other as a fish
way or fish ladder a proper pathway for moving fishes. In this article
we first examine the surrounding environment and then Ghazal Ozon
River and preserving the aquatics.