Implementation of Adder-Subtracter Design with VerilogHDL

According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

Authors:

• May Phyo Thwal
• Khin Htay Kyi
• Kyaw Swar Soe

Keywords:

• Addition
• arithmetic logic unit
• carry look-ahead adder
• Verilog HDL.

References:

[1] Andrew S. Tanenbaum, Structure Computer Organization, Fourth
edition, Prentice_Hall, Inc., 1999.
[2] Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synpaper,
Sun Microsystems, Inc., 1996.
[3] William Stallings, Computer Organization & Architecture, Sixth edition.
[4] David A. Patterson, John L. Hennessy, Computer Organization and
Design, (The Hardware /Software Interface), Third edition, Elsevier Inc.,
2005.