A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors.

Authors:

• A. Dandapat
• S. Ghosal
• P. Sarkar
• D. Mukhopadhyay

Keywords:

• Binary multiplier
• Compressors
• Counter
• Column adder
• Low power.

References:

[1] V.G. Oklobdzija, D. Villeger, S.S. Liu. "A method for speed optimized
partial product reduction and generation of fast parallel multipliers using
an algorithmic approach". IEEE Trans. on Computers, vol. 45, No. 3,
March 1996.
[2] V. Oklobdzija. High speed VLSI arithmatic unit: Adders and
Multipliers. in "Design of high performance microprocessor circuits",
Ed. A. Chandrakasan, IEEE Press, 2000.
[3] A. Dandapat, P. Bose, Sayan Ghosh, Pikul Sarkar, and D.
Mukhopadhyay, "Design of an Application Specific Low-Power High
Performance Carry Save 4-2 Compressor" in IEEE VLSI Design and
Test Symposium 2007, VDAT-07, pp.360, 2007.
[4] S. F. Hsiao, M.R. Jiang and J.S Yeh. "Design of high speed low power
3-2 counter and 4-2 compressor for fast multipliers". Electronics
Letters, vol. 34, No. 4, pp 341-343, 1998.
[5] Jiangmin Gu, Chip-Hong Chang. "Ultra low voltage low power 4-2
compressor for high speed multiplications". Circuits and Systems, 2003.
ISCAS -03. Proceedings of the International Symposium, vol. 5, pp.
v321-v324, May 2003.
[6] D. Radhakrishnan and A.P Preethy. "Low power CMOS pass logic 4-2
compressor for high speed multiplication". Proc. of the 43th IEEE
Midwest Symposium on Circuit and Systems, vol. 3, pp 1296-1298,
2000.
[7] K. Prasad and K. K. Parthi. "Low power 4-2 and 5-2 compressor". Proc.
of the 35th Asilomar Conf. on Signals, Systems and Computors, vol. 1,
pp. 129-133, 2001.
[8] C. F. Law, S. S. Rofail and K. S.Yeo, "Low-power circuit
implementation for partial product addition using pass transistor logic,"
in IEE proceedings- Circuits Devices Systems, vol 146, No-3, June
1999.
[9] V. G. Oklobdzija, D. Villeger, and S. S. Liu, "A method for speed
optimization partial product reduction and generation of fast multipliers
using algorithmic approach," IEEE transaction on Computers, vol. 45.
No. 3 March 1993.
[10] A. Dandapat, N. N. Majumder, P. Bose, D. Mukhopadhyay, "power
Performance Optimization of an 8-bit Multiplier Using Transmission
gates", in International Conference on Computers and Devices for
Communication,2006, pp-cis 95, Dec 2006.
[11] Changbo Long; Lei He; " Distributed sleep transistor network for power
reduction," in IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol-12, pp. 937-946, Sept 2006.
[12] Tschanz, J.W.; Narendra, S.G.; Ye, Y.; Bloechel, B.A.; Borkar, S.; De,
V.; "Dynamic sleep transistor and body bias for active leakage power
control of microprocessors,"in IEEE IEEE journal of Solid-State
Circuits, vol-38, pp. 1838 - 1845, Nov. 2003.