Complementary Energy Path Adiabatic Logic based Full Adder Circuit
In this paper, we present the design and experimental
evaluation of complementary energy path adiabatic logic (CEPAL)
based 1 bit full adder circuit. A simulative investigation on the
proposed full adder has been done using VIRTUOSO SPECTRE
simulator of cadence in 0.18μm UMC technology and its
performance has been compared with the conventional CMOS full
adder circuit. The CEPAL based full adder circuit exhibits the energy
saving of 70% to the conventional CMOS full adder circuit, at 100
MHz frequency and 1.8V operating voltage.
[1] Cihun-siyong Alex Gong, Muh- Tihan Shiue, Ci-Tong Hong, And Kai-
Wen Yao, "Analysis and Design of an Efficient Irreversible Energy
Recovery Logic in 0.18-╬╝m CMOS", IEEE Transactions On Circuits
and Systms- I: Regular Papers, vol.55, no.9,pp.2595-2607,October
2008.
[2] N.S.S. Reddy, M. Satyam,and K.L. Kishore, "Cascadable Adiabatic
Logic Circuits for Low-Power Applications", IET Circuits Devices
Syst., vol. 2, no. 6, pp. 518-526. June 2008.
[3] Yibin Ye, And Kaushik Roy, "QSERL: Quasi-static Energy Recovery
Logic", IEEE Journal of Solid-state Circuits, vol.36. no.2, pp. 239-248,
Feburary 2001.
[4] Sompong Wisetphanichkij, Kobchai Dejhan, "The Combinational and
Sequential Adiabatic Circuit Design and Its Applications", Circuits Syst
Signal Process ,vol.28,pp. 523-534, 2009.
[5] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C.
Chou, "Low-power digital systems based on adiabatic-switching
principles," IEEE Trans. VLSI Syst., vol. 2, pp. 398-407, Dec. 1994.
[6] Vivek K. De and James D. Meindl, "Opportunities for non-Dissipative
Computation", in Conf. 1995 IEEE, pp. 297-300.
[7] Y. Moon and D.-K. Jeong, "An efficient charge recovery logic circuit,"
IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 514-522, Apr. 1996.
[8] Conrad H. Ziesler, and Marios C. Papaefthymiou, "A True Single-Phase
Energy-Recovery Multiplier",Suhwan Kim, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, vol. 11, no. 2,pp.52-63,April
2003.
[9] Mehrdad Khatir, Alireza Ejlali, Amir Moradi,"Improving The Energy
Efficiency of Reversible Logic Circuits by The Combined Use of
Adiabatic Styles", Integration the VLSI Journal, Elsevier, vol.44, pp. 12-
21,2011.
[10] Visvesh S. Sathe, Juang-ying Chueh, and Marios C.
Papefthymiou,"Energy Efficient GHz-Class Charge Recovery Logic",
IEEE Journal of Solid-state Circuits, vol.42, No.1, pp. 38-47,January
2007.
[11] Myeong-Eun Hwang, Arijit Raychowdhury, and Kaushik Roy,"Energy-
Recovery Techniques to Reduce On-Chip Power Density in Molecular
Nanotechnologies", IEEE Transactions on Circuits and SystemsÔÇöi:
regular Papers, vol. 52, No. 8, pp. 1580-1589, ,August 2005.
[12] Nazarul Anuar, yashuhiro Takahashi, and Toshikazu Sekine, "LSI
implementation of a low-power 4x4-bit array two-phase clocked
adiabatic static CMOS logic multiplier",Microelectronics Journal,
Elsevier, vol.43, pp. 244-249, 2012.
[13] D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of
Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2003.
[14] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwati,"New
Design Methodologies for High Speed Mixed- Mode Full Adder
Circuit", International Journal of VLSI and Communication Systems
(VLSICS), AIRCC Publication, vol. 2, no. 2, pp. 78-98,2011.
[15] N. H. E.Weste and D. Harris, CMOS VLSI Design-A Circuits and
Systems Perspective, 3rd ed. Reading, MA: Addison-Wesley, 2004.
[16] Adarsh Kumar Agarwal, S. Wairya, R.K. Nagaria and S. Tiwari, "A
New Mixed Gate Diffusion Input Full Adder Topology for High Speed
Low Power Digital Circuits", World Applied Science Journal
(WASJ),Special Issue of Computer & IT, vol. 7, pp. 138-144,2009.
[17] Shipra Upadhyay, R.A. Mishra and R.K. Nagaria, "Comparative
Performance of Irreversible Adiabatic Logic Circuits for Low Power
VLSI Design," Proc. ICIAICT-2012 International Conference on
Innovations and Advancements in Information and Communication
Technology ICIAICT, GBU Greater Noida, vol. 3, pp. 379-386,2012.
[1] Cihun-siyong Alex Gong, Muh- Tihan Shiue, Ci-Tong Hong, And Kai-
Wen Yao, "Analysis and Design of an Efficient Irreversible Energy
Recovery Logic in 0.18-╬╝m CMOS", IEEE Transactions On Circuits
and Systms- I: Regular Papers, vol.55, no.9,pp.2595-2607,October
2008.
[2] N.S.S. Reddy, M. Satyam,and K.L. Kishore, "Cascadable Adiabatic
Logic Circuits for Low-Power Applications", IET Circuits Devices
Syst., vol. 2, no. 6, pp. 518-526. June 2008.
[3] Yibin Ye, And Kaushik Roy, "QSERL: Quasi-static Energy Recovery
Logic", IEEE Journal of Solid-state Circuits, vol.36. no.2, pp. 239-248,
Feburary 2001.
[4] Sompong Wisetphanichkij, Kobchai Dejhan, "The Combinational and
Sequential Adiabatic Circuit Design and Its Applications", Circuits Syst
Signal Process ,vol.28,pp. 523-534, 2009.
[5] W. C. Athas, L. J. Svensson, J. G. Koller, N. Tzartzanis, and E. Y.-C.
Chou, "Low-power digital systems based on adiabatic-switching
principles," IEEE Trans. VLSI Syst., vol. 2, pp. 398-407, Dec. 1994.
[6] Vivek K. De and James D. Meindl, "Opportunities for non-Dissipative
Computation", in Conf. 1995 IEEE, pp. 297-300.
[7] Y. Moon and D.-K. Jeong, "An efficient charge recovery logic circuit,"
IEEE J. Solid-State Circuits, vol. 31, no. 4, pp. 514-522, Apr. 1996.
[8] Conrad H. Ziesler, and Marios C. Papaefthymiou, "A True Single-Phase
Energy-Recovery Multiplier",Suhwan Kim, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, vol. 11, no. 2,pp.52-63,April
2003.
[9] Mehrdad Khatir, Alireza Ejlali, Amir Moradi,"Improving The Energy
Efficiency of Reversible Logic Circuits by The Combined Use of
Adiabatic Styles", Integration the VLSI Journal, Elsevier, vol.44, pp. 12-
21,2011.
[10] Visvesh S. Sathe, Juang-ying Chueh, and Marios C.
Papefthymiou,"Energy Efficient GHz-Class Charge Recovery Logic",
IEEE Journal of Solid-state Circuits, vol.42, No.1, pp. 38-47,January
2007.
[11] Myeong-Eun Hwang, Arijit Raychowdhury, and Kaushik Roy,"Energy-
Recovery Techniques to Reduce On-Chip Power Density in Molecular
Nanotechnologies", IEEE Transactions on Circuits and SystemsÔÇöi:
regular Papers, vol. 52, No. 8, pp. 1580-1589, ,August 2005.
[12] Nazarul Anuar, yashuhiro Takahashi, and Toshikazu Sekine, "LSI
implementation of a low-power 4x4-bit array two-phase clocked
adiabatic static CMOS logic multiplier",Microelectronics Journal,
Elsevier, vol.43, pp. 244-249, 2012.
[13] D. A. Hodges, H. G. Jackson, and R. A. Saleh, Analysis and Design of
Digital Integrated Circuits, 3rd ed. New York: McGraw-Hill, 2003.
[14] Subodh Wairya, Rajendra Kumar Nagaria and Sudarshan Tiwati,"New
Design Methodologies for High Speed Mixed- Mode Full Adder
Circuit", International Journal of VLSI and Communication Systems
(VLSICS), AIRCC Publication, vol. 2, no. 2, pp. 78-98,2011.
[15] N. H. E.Weste and D. Harris, CMOS VLSI Design-A Circuits and
Systems Perspective, 3rd ed. Reading, MA: Addison-Wesley, 2004.
[16] Adarsh Kumar Agarwal, S. Wairya, R.K. Nagaria and S. Tiwari, "A
New Mixed Gate Diffusion Input Full Adder Topology for High Speed
Low Power Digital Circuits", World Applied Science Journal
(WASJ),Special Issue of Computer & IT, vol. 7, pp. 138-144,2009.
[17] Shipra Upadhyay, R.A. Mishra and R.K. Nagaria, "Comparative
Performance of Irreversible Adiabatic Logic Circuits for Low Power
VLSI Design," Proc. ICIAICT-2012 International Conference on
Innovations and Advancements in Information and Communication
Technology ICIAICT, GBU Greater Noida, vol. 3, pp. 379-386,2012.
@article{"International Journal of Electrical, Electronic and Communication Sciences:56648", author = "Shipra Upadhyay and R. K. Nagaria and R. A. Mishra", title = "Complementary Energy Path Adiabatic Logic based Full Adder Circuit", abstract = "In this paper, we present the design and experimental
evaluation of complementary energy path adiabatic logic (CEPAL)
based 1 bit full adder circuit. A simulative investigation on the
proposed full adder has been done using VIRTUOSO SPECTRE
simulator of cadence in 0.18μm UMC technology and its
performance has been compared with the conventional CMOS full
adder circuit. The CEPAL based full adder circuit exhibits the energy
saving of 70% to the conventional CMOS full adder circuit, at 100
MHz frequency and 1.8V operating voltage.", keywords = "Adiabatic, CEPAL, full adder, power clock", volume = "6", number = "6", pages = "560-6", }
