A High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree
Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
[1] R.P. Brent and H.T. Kung, "A regular layout for parallel adders", IEEE
Trans. Comput., vol. C-31, pp. 260-264, Mar. 1982.
[2] A. Goldovsky, B. Patel and B. Schulte, "Design and implementation of
a 16 by 16 low-power two's complement multiplier", ISCAS 2000
Geneva, vol. 5, pp. 345-348.
[3] G. Goto., et. al., "A 4.1-ns compact 54*54-b multiplier utilizing signselect
Booth encoders", IEEE J. Solid-State Circuits, vol. 32, pp. 1676-
1682, Nov. 1997.
[4] X. Huang, et. al., "High-performance VLSI multiplier with a new
redundant binary coding", Journal of VLSI Signal processing, vol. 3,
pp. 283-291, Oct. 1991.
[5] P. Giopeen, "Novel and Efficient four to two counters", ISCAS 2000
Geneva, vol. 5, pp. 312-319.
[6] D. Kudeeth., "Implementation of low-power multipliers", Journal of
low-power electronics, vol. 2, 5-11, 2006.
[7] K.H. Ching, "A novel carry-lookahead adder", Proc. International
symposium low-power electronics and design, 1998.
[8] H. Lee, "A High-Speed Booth Multiplier", ICCS 2002.
[9] T.Y. Tang, and C.S. Choy, "Design of self-timed asynchronous Booth's
multiplier", in Proc. Asia South Pacific Design Automation Conf., Jan
2000, pp. 15-19.
[10] K. Numba and H. Itu, "High-speed design for Wallace multiplier",
ISSCC 2003.
[11] Y.N. Ching, "Low-power high-speed multipliers", IEEE Transactions
on Computers, vol. 54, no. 3, pp. 355-361, 2005.
[12] M. Sheplie, "High performance array multiplier", IEEE transactions on
very large scale integration systems, vol. 12, no. 3, pp. 320-325, 2004.
[1] R.P. Brent and H.T. Kung, "A regular layout for parallel adders", IEEE
Trans. Comput., vol. C-31, pp. 260-264, Mar. 1982.
[2] A. Goldovsky, B. Patel and B. Schulte, "Design and implementation of
a 16 by 16 low-power two's complement multiplier", ISCAS 2000
Geneva, vol. 5, pp. 345-348.
[3] G. Goto., et. al., "A 4.1-ns compact 54*54-b multiplier utilizing signselect
Booth encoders", IEEE J. Solid-State Circuits, vol. 32, pp. 1676-
1682, Nov. 1997.
[4] X. Huang, et. al., "High-performance VLSI multiplier with a new
redundant binary coding", Journal of VLSI Signal processing, vol. 3,
pp. 283-291, Oct. 1991.
[5] P. Giopeen, "Novel and Efficient four to two counters", ISCAS 2000
Geneva, vol. 5, pp. 312-319.
[6] D. Kudeeth., "Implementation of low-power multipliers", Journal of
low-power electronics, vol. 2, 5-11, 2006.
[7] K.H. Ching, "A novel carry-lookahead adder", Proc. International
symposium low-power electronics and design, 1998.
[8] H. Lee, "A High-Speed Booth Multiplier", ICCS 2002.
[9] T.Y. Tang, and C.S. Choy, "Design of self-timed asynchronous Booth's
multiplier", in Proc. Asia South Pacific Design Automation Conf., Jan
2000, pp. 15-19.
[10] K. Numba and H. Itu, "High-speed design for Wallace multiplier",
ISSCC 2003.
[11] Y.N. Ching, "Low-power high-speed multipliers", IEEE Transactions
on Computers, vol. 54, no. 3, pp. 355-361, 2005.
[12] M. Sheplie, "High performance array multiplier", IEEE transactions on
very large scale integration systems, vol. 12, no. 3, pp. 320-325, 2004.
@article{"International Journal of Electrical, Electronic and Communication Sciences:59469", author = "P. Asadee", title = "A High-Speed Multiplication Algorithm Using Modified Partial Product Reduction Tree", abstract = "Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.", keywords = "adder, CMOS, counter, Dadda tree, encoder.", volume = "4", number = "3", pages = "589-7", }