Abstract: In this paper, the transient device performance analysis
of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been
evaluated. 3-D Bohm Quantum Potential (BQP) transport device
simulation has been used to evaluate the delay and power dissipation
performance. GI-JLT has a number of desirable device parameters
such as reduced propagation delay, dynamic power dissipation,
power and delay product, intrinsic gate delay and energy delay
product as compared to Gate-all-around transistors GAA-JLT. In
addition to this, various other device performance parameters namely,
on/off current ratio, short channel effects (SCE), transconductance
Generation Factor (TGF) and unity gain cut-off frequency (fT ) and
subthreshold slope (SS) of the GI-JLT and GAA-JLT have been
analyzed and compared. GI-JLT shows better device performance
characteristics than GAA-JLT for low power and high frequency
applications, because of its larger gate electrostatic control on the
device operation.
Abstract: Anultra-low power capacitor less low-dropout voltage
regulator with improved transient response using gain enhanced feed
forward path compensation is presented in this paper. It is based on a
cascade of a voltage amplifier and a transconductor stage in the feed
forward path with regular error amplifier to form a composite gainenhanced
feed forward stage. It broadens the gain bandwidth and thus
improves the transient response without substantial increase in power
consumption. The proposed LDO, designed for a maximum output
current of 100 mA in UMC 180 nm, requires a quiescent current of
69 )A. An undershot of 153.79mV for a load current changes from
0mA to 100mA and an overshoot of 196.24mV for current change of
100mA to 0mA. The settling time is approximately 1.1 )s for the
output voltage undershooting case. The load regulation is of 2.77
)V/mA at load current of 100mA. Reference voltage is generated by
using an accurate band gap reference circuit of 0.8V.The costly
features of SOC such as total chip area and power consumption is
drastically reduced by the use of only a total compensation
capacitance of 6pF while consuming power consumption of 0.096
mW.
Abstract: CNFET has emerged as an alternative material to
silicon for high performance, high stability and low power SRAM
design in recent years. SRAM functions as cache memory in
computers and many portable devices. In this paper, a new SRAM
cell design based on CNFET technology is proposed. The proposed
SRAM cell design for CNFET is compared with SRAM cell designs
implemented with the conventional CMOS and FinFET in terms of
speed, power consumption, stability, and leakage current. The
HSPICE simulation and analysis show that the dynamic power
consumption of the proposed 8T CNFET SRAM cell’s is reduced
about 48% and the SNM is widened up to 56% compared to the
conventional CMOS SRAM structure at the expense of 2% leakage
power and 3% write delay increase.
Abstract: In this study, we developed a complementary electrochromic device consisting of WO3 and NiO films fabricated by rf-magnetron sputtered. The electrochromic properties of WO3 and NiO films were investigated using cyclic voltammograms (CV), performed on WO3 and NiO films immersed in an electrolyte of 1 M LiClO4 in propylene carbonate (PC). Optical and electrochemical of the films, as a function of coloration–bleaching cycle, were characterized using an UV-Vis-NIR spectrophotometer and cyclic voltammetry (CV). After investigating the properties of WO3 film, NiO film, and complementary electrochromic devices, we concluded that this device provides good reversibility, low power consumption of -2.5 V in color state, high variation of transmittance of 58.96%, changes in optical density of 0.81 and good memory effect under open-circuit conditions. In addition, electrochromic component penetration rate can be retained below 20% within 24h, showing preferred memory features; however, component coloring and bleaching response time are about 33s.
Abstract: Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characterized it in terms of read and write delay, read and write noise margins, Data Retention Voltage and Leakage Current. Read Decoupling improves the Read Noise Margin and static power dissipation is reduced by using Dual-Vt transistors. The results obtained are compared with existing 6T, 8T, 9T SRAM Cells, which shows the superiority of the proposed design. The Cell is designed and simulated in TSPICE using 90nm CMOS process.
Abstract: An adder is one of the most integral component of a digital system like a digital signal processor or a microprocessor. Being an extremely computationally intensive part of a system, the optimization for speed and power consumption of the adder is of prime importance. In this paper we have designed a 1 bit full adder cell based on dynamic TSPC logic to achieve high speed operation. A high threshold voltage sleep transistor is used to reduce the static power dissipation in standby mode. The circuit is designed and simulated in TSPICE using TSMC 180nm CMOS process. Average power consumption, delay and power-delay product is measured which showed considerable improvement in performance over the existing full adder designs.
Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: The network designing and data modeling developments which are the two significant research tasks in direction to tolerate power control of Microgrid concluded using IEC 61850 data models and facilities. The current casing areas of IEC 61580 include infrastructures in substation automation systems, among substations and to DERs. So, for LV microgrid power control, previously using the IEC 61850 amenities to control the smart electrical devices, we have to model those devices as IEC 61850 data models and design a network topology to maintenance all-in-one communiqué amid those devices. In adding, though IEC 61850 assists modeling a portion by open-handed several object models for common functions similar measurement, metering, monitoring…etc., there are motionless certain missing smithereens for building a multiplicity of functions for household appliances like tuning the temperature of an electric heater or refrigerator.
Abstract: Power dissipation due to leakage current in the digital circuits is a biggest factor which is considered specially while designing nanoscale circuits. This paper is exploring the ideas of reducing leakage current in static CMOS circuits by stacking the transistors in increasing numbers. Clearly it means that the stacking of OFF transistors in large numbers result a significant reduction in power dissipation. Increase in source voltage of NMOS transistor minimizes the leakage current. Thus stacking technique makes circuit with minimum power dissipation losses due to leakage current. Also some of digital circuits such as full adder, D flip flop and 6T SRAM have been simulated in this paper, with the application of reduction technique on ‘cadence virtuoso tool’ using specter at 45nm technology with supply voltage 0.7V.
Abstract: This paper presents an efficient burst error spreading tool. Also, it studies a vital issue in wireless communications, which is the transmission of images over wireless networks. IEEE ZigBee 802.15.4 is a short-range communication standard that could be used for small distance multimedia transmissions. In fact, the ZigBee network is a Wireless Personal Area Network (WPAN), which needs a strong interleaving mechanism for protection against error bursts. Also, it is low power technology and utilized in the Wireless Sensor Networks (WSN) implementation. This paper presents the chaotic interleaving scheme as a data randomization tool for this purpose. This scheme depends on the chaotic Baker map. The mobility effects on the image transmission are studied with different velocity through utilizing the Jakes’ model. A comparison study between the proposed chaotic interleaving scheme and the traditional block and convolutional interleaving schemes for image transmission over a correlated fading channel is presented. The simulation results show the superiority of the proposed chaotic interleaving scheme over the traditional schemes.
Abstract: This paper presents the development of a 38.5 kS/s 10-bit low power SAR ADC which is realized in MIMOS’s 0.35 µm CMOS process. The design uses a resistive DAC, a dynamic comparator with pre-amplifier and SAR digital logic to create 10 effective bits while consuming less than 7.8 mW with a 3.3 V power supply.
Abstract: In this paper, the design of wide-swing constant transconductance (gm) bias circuit that generates bias voltage for low-noise amplifier (LNA) circuit design by using an off-chip resistor is demonstrated. The overall transconductance (Gm) generated by the constant gm bias circuit is important to maintain the overall gain and noise figure of the LNA circuit. Therefore, investigation is performed to study the variation in Gm with process, temperature and supply voltage (PVT). Temperature and supply voltage are swept from -10 °C to 85 °C and 1.425 V to 1.575 V respectively, while the process conditions are also varied to the extreme and the gm variation is eventually concluded at between -3 % to 7 %. With the slight variation in the gm value, through simulation, at worst condition of state SS, we are able to attain a conversion gain (S21) variation of -3.10 % and a noise figure (NF) variation of 18.71 %. The whole constant gm circuit draws approximately 100 µA from a 1.5V supply and is designed based on 0.13 µm CMOS process.
Abstract: This paper presents the design and implementation of a fully integrated Capacitance-to-Voltage Converter (CVC) as the analog front-end for magnetometer interface IC. The application demands very low power solution operating in the frequency of around 20 KHz. The design adapts low power architecture to create low noise electronic interface for Capacitive Micro-machined Lorentz force magnetometer sensor. Using a 0.18-μm CMOS process, simulation results of this interface IC show that the proposed CVC can provide 33 dB closed loop gain, 20 nV/√Hz input referred noise at 20 KHz, while consuming 65 μA current from 1.8-V supply.
Abstract: The goal of this paper is to examine the effects of laser
radiation on the skin wound healing using infrared thermography as
non-invasive method for the monitoring of the skin temperature
changes during laser treatment. Thirty Wistar rats were used in this
study. A skin lesion was performed at the leg on all rats. The animals
were exposed to laser radiation (λ = 670 nm, P = 15 mW, DP = 16.31
mW/cm2) for 600 s. Thermal images of wound were acquired before
and after laser irradiation. The results have demonstrated that the
tissue temperature decreases from 35.5±0.50°C in the first treatment
day to 31.3±0.42°C after the third treatment day. This value is close
to the normal value of the skin temperature and indicates the end of
the skin repair process. In conclusion, the improvements in the
wound healing following exposure to laser radiation have been
revealed by infrared thermography.
Abstract: This paper aims to present the design, fabrication and test of a novel piezoelectric actuated, check-valves embedded micropump having the advantages of miniature size, light weight and low power consumption. This device is designed to pump gases and liquids with the capability of performing the self-priming and bubble-tolerant work mode by maximizing the stroke volume of the membrane as well as the compression ratio via minimization of the dead volume of the micropump chamber and channel. By experiment apparatus setup, we can get the real-time values of the flow rate of micropump, the displacement of the piezoelectric actuator and the deformation of the check valve, simultaneously. The micropump with check valve 0.4 mm in thickness obtained higher output performance under the sinusoidal waveform of 120 Vpp. The micropump achieved the maximum pumping rates of 42.2 ml/min and back pressure of 14.0 kPa at the corresponding frequency of 28 and 20 Hz. The presented micropump is able to pump gases with a pumping rate of 196 ml/min at operating frequencies of 280 Hz under the sinusoidal waveform of 120 Vpp.
Abstract: Wireless Sensor Networks consist of inexpensive, low power sensor nodes deployed to monitor the environment and collect
data. Gathering information in an energy efficient manner is a critical aspect to prolong the network lifetime. Clustering algorithms have an advantage of enhancing the network lifetime. Current clustering algorithms usually focus on global re-clustering and local re-clustering separately. This paper, proposed a combination of those two reclustering methods to reduce the energy consumption of the network. Furthermore, the proposed algorithm can apply to homogeneous as well as heterogeneous wireless sensor networks. In addition, the cluster head rotation happens, only when its energy drops below a dynamic threshold value computed by the algorithm. The simulation result shows that the proposed algorithm prolong the network lifetime compared to existing algorithms.
Abstract: There are multiple ways to implement a decimator
filter. This paper addresses usage of CIC (cascaded-integrator-comb)
filter and HB (half band) filter as the decimator filter to reduce the
frequency sample rate by factor of 64 and detail of the
implementation step to realize this design in hardware. Low power
design approach for CIC filter and half band filter will be discussed.
The filter design is implemented through MATLAB system
modeling, ASIC (application specific integrated circuit) design flow
and verified using a FPGA (field programmable gate array) board
and MATLAB analysis.
Abstract: In this paper we introduce an ultra low power CMOS
LC oscillator and analyze a method to design a low power low phase
noise complementary CMOS LC oscillator. A 1.8GHz oscillator is
designed based on this analysis. The circuit has power supply equal
to 1.1 V and dissipates 0.17 mW power. The oscillator is also
optimized for low phase noise behavior. The oscillator phase noise is
-126.2 dBc/Hz and -144.4 dBc/Hz at 1 MHz and 8 MHz offset
respectively.
Abstract: A SCADA (Supervisory Control And Data
Acquisition) system is an industrial control and monitoring system for
national infrastructures. The SCADA systems were used in a closed
environment without considering about security functionality in the
past. As communication technology develops, they try to connect the
SCADA systems to an open network. Therefore, the security of the
SCADA systems has been an issue. The study of key management for
SCADA system also has been performed. However, existing key
management schemes for SCADA system such as SKE(Key
establishment for SCADA systems) and SKMA(Key management
scheme for SCADA systems) cannot support broadcasting
communication. To solve this problem, an Advanced Key
Management Architecture for Secure SCADA Communication has
been proposed by Choi et al.. Choi et al.-s scheme also has a problem
that it requires lots of computational cost for multicasting
communication. In this paper, we propose an enhanced scheme which
improving computational cost for multicasting communication with
considering the number of keys to be stored in a low power
communication device (RTU).
Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.