Transient Enhanced LDO Voltage Regulator with Improved Feed Forward Path Compensation
Anultra-low power capacitor less low-dropout voltage
regulator with improved transient response using gain enhanced feed
forward path compensation is presented in this paper. It is based on a
cascade of a voltage amplifier and a transconductor stage in the feed
forward path with regular error amplifier to form a composite gainenhanced
feed forward stage. It broadens the gain bandwidth and thus
improves the transient response without substantial increase in power
consumption. The proposed LDO, designed for a maximum output
current of 100 mA in UMC 180 nm, requires a quiescent current of
69 )A. An undershot of 153.79mV for a load current changes from
0mA to 100mA and an overshoot of 196.24mV for current change of
100mA to 0mA. The settling time is approximately 1.1 )s for the
output voltage undershooting case. The load regulation is of 2.77
)V/mA at load current of 100mA. Reference voltage is generated by
using an accurate band gap reference circuit of 0.8V.The costly
features of SOC such as total chip area and power consumption is
drastically reduced by the use of only a total compensation
capacitance of 6pF while consuming power consumption of 0.096
mW.
[1] G. Patounakis, Y. W. Li, and K. Shepard. A fully integrated on-chip DCDC
conversion and power management system. IEEE Journal of Solid-
State Circuits, 39(3):443–451, March 2004.
[2] D. Evans, M. McConnel, P. Kawamura, and L. Krug. SoC integration
challenges for a power management/analog baseband ic for 3G wireless
chipsets. Proc. Int. Symp. Power Semicond.Devices ICs, pages 77–80,
May 2004.
[3] P. Hazucha, T. Karnik, A. Bloechel, C. Parsons, D. Finan, and S.
Brokar. Area-efficient linear regulator with ultra-fast load regulation.
IEEE Journal of Solid-State Circuits, 40(4):933–940,April 2005.
[4] Tsz Yin Man, Philip K. Mok, and M. Chan. A high slew-rate push-pull
output amplifier for low-quiescent current low-dropout regulators with
transient-response improvement. IEEE Transactions on Circuits and
Systems – II: Express Briefs, 54(9):755–759, September 2007.
[5] S. K. Lau, P. K. T. Mok, and K. N. Leung. A low-dropout regulator for
SoC with q-reduction.IEEE Journal Solid-State Circuits, 42(3):658–664,
March 2007.
[6] P.R. Surkanti, A. Garimella, and P.M. Furth. Pole-zero analysis of multistage
amplifiers: A tutorial overview. IEEE 54th Int. Midwest Symp. on
Circuits and Systems, pages 1–4, August 2011.
[7] Ka Chun Kwok and P. K. T. Mok. Pole-zero tracking frequency
compensation for low dropout regulator. IEEE Int. Symp. on Circuits
and Systems, 4:735–738, May 2002.
[8] Ka Nang Leung and Philip K. Mok. A capacitor-free CMOS lowdropout
regulator with dampingfactor-control frequency compensation.
IEEE Journal of Solid-State Circuits, 38(10):1691–1702,October 2003.
[9] Ka Nang Leung and Philip K. Mok. Analysis of multistage amplifier –
frequency compensation.IEEE Trans. Circuits Syst. I, 48:1041–1056,
September 2001.
[10] Xin Ming, Qiang Li, Ze-kun Zhou, and Bo Zhang. An ultrafast
adaptively biased capacitorless LDO with dynamic charging control.
IEEE Trans. on Circuits and Systems – II: Express Briefs,59(1):40–44,
January2012.
[11] V.R. Saari "Low Power high drive CMOS operational amplifiers”,
IEEEJ J. Solid-State circuits, vol. SC-18, pp. 121-127, 1983.
[12] R.J. Baker,H.W.Li,and D.E Boyce,CMOS Circuit Design,Layout and
Simulation.piscataway,NJ:IEEE Press,1998,chap 26.
[13] Bazes, M., "Two novel fully complementary self-biased CMOS
differential amplifiers," Solid-State Circuits, IEEE Journal of , vol.26,
no.2, pp.165,168, Feb 1991.
[14] Zhan, Chenchang, and Wing-Hung Ki, "A high-precision low-voltage
low dropout regulator for SoC with adaptive biasing”, Circuits and
Systems, 2009. ISCAS 2009. IEEE International Symposium on. IEEE,
2009.
[15] Chong, S. S., and P. K. Chan, "A quiescent power-aware low-voltage
output capacitorless low dropout regulator for SOC applications”,
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on.
IEEE, 2011.
[16] X. Ming, Q. Li, Z. Zhou, and B. Zhang, "An ultrafast adaptively biased
capacitorless LDO with dynamic charging control”, IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 59, no. 1, pp. 40–44, Jan. 2012.
[17] Young-Il Kim; Sang-sun Lee, "A Capacitor less LDO Regulator with
Fast Feedback Technique and Low-Quiescent Current Error Amplifier”,
Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.60,
no.6, pp.326,330, June 2013.
[18] Fathipour, Rasoul, et al., "High slew rate current mode transconductance
error amplifier for low quiescent current output-capacitorless CMOS
LDO regulator”, Integration, the VLSI Journal 47.2 (2014): 204-212.
[1] G. Patounakis, Y. W. Li, and K. Shepard. A fully integrated on-chip DCDC
conversion and power management system. IEEE Journal of Solid-
State Circuits, 39(3):443–451, March 2004.
[2] D. Evans, M. McConnel, P. Kawamura, and L. Krug. SoC integration
challenges for a power management/analog baseband ic for 3G wireless
chipsets. Proc. Int. Symp. Power Semicond.Devices ICs, pages 77–80,
May 2004.
[3] P. Hazucha, T. Karnik, A. Bloechel, C. Parsons, D. Finan, and S.
Brokar. Area-efficient linear regulator with ultra-fast load regulation.
IEEE Journal of Solid-State Circuits, 40(4):933–940,April 2005.
[4] Tsz Yin Man, Philip K. Mok, and M. Chan. A high slew-rate push-pull
output amplifier for low-quiescent current low-dropout regulators with
transient-response improvement. IEEE Transactions on Circuits and
Systems – II: Express Briefs, 54(9):755–759, September 2007.
[5] S. K. Lau, P. K. T. Mok, and K. N. Leung. A low-dropout regulator for
SoC with q-reduction.IEEE Journal Solid-State Circuits, 42(3):658–664,
March 2007.
[6] P.R. Surkanti, A. Garimella, and P.M. Furth. Pole-zero analysis of multistage
amplifiers: A tutorial overview. IEEE 54th Int. Midwest Symp. on
Circuits and Systems, pages 1–4, August 2011.
[7] Ka Chun Kwok and P. K. T. Mok. Pole-zero tracking frequency
compensation for low dropout regulator. IEEE Int. Symp. on Circuits
and Systems, 4:735–738, May 2002.
[8] Ka Nang Leung and Philip K. Mok. A capacitor-free CMOS lowdropout
regulator with dampingfactor-control frequency compensation.
IEEE Journal of Solid-State Circuits, 38(10):1691–1702,October 2003.
[9] Ka Nang Leung and Philip K. Mok. Analysis of multistage amplifier –
frequency compensation.IEEE Trans. Circuits Syst. I, 48:1041–1056,
September 2001.
[10] Xin Ming, Qiang Li, Ze-kun Zhou, and Bo Zhang. An ultrafast
adaptively biased capacitorless LDO with dynamic charging control.
IEEE Trans. on Circuits and Systems – II: Express Briefs,59(1):40–44,
January2012.
[11] V.R. Saari "Low Power high drive CMOS operational amplifiers”,
IEEEJ J. Solid-State circuits, vol. SC-18, pp. 121-127, 1983.
[12] R.J. Baker,H.W.Li,and D.E Boyce,CMOS Circuit Design,Layout and
Simulation.piscataway,NJ:IEEE Press,1998,chap 26.
[13] Bazes, M., "Two novel fully complementary self-biased CMOS
differential amplifiers," Solid-State Circuits, IEEE Journal of , vol.26,
no.2, pp.165,168, Feb 1991.
[14] Zhan, Chenchang, and Wing-Hung Ki, "A high-precision low-voltage
low dropout regulator for SoC with adaptive biasing”, Circuits and
Systems, 2009. ISCAS 2009. IEEE International Symposium on. IEEE,
2009.
[15] Chong, S. S., and P. K. Chan, "A quiescent power-aware low-voltage
output capacitorless low dropout regulator for SOC applications”,
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on.
IEEE, 2011.
[16] X. Ming, Q. Li, Z. Zhou, and B. Zhang, "An ultrafast adaptively biased
capacitorless LDO with dynamic charging control”, IEEE Trans.
Circuits Syst. II, Exp. Briefs, vol. 59, no. 1, pp. 40–44, Jan. 2012.
[17] Young-Il Kim; Sang-sun Lee, "A Capacitor less LDO Regulator with
Fast Feedback Technique and Low-Quiescent Current Error Amplifier”,
Circuits and Systems II: Express Briefs, IEEE Transactions on , vol.60,
no.6, pp.326,330, June 2013.
[18] Fathipour, Rasoul, et al., "High slew rate current mode transconductance
error amplifier for low quiescent current output-capacitorless CMOS
LDO regulator”, Integration, the VLSI Journal 47.2 (2014): 204-212.
@article{"International Journal of Electrical, Electronic and Communication Sciences:68145", author = "Suresh Alapati and Sreehari Rao Patri and K. S. R. Krishna Prasad", title = "Transient Enhanced LDO Voltage Regulator with Improved Feed Forward Path Compensation", abstract = "Anultra-low power capacitor less low-dropout voltage
regulator with improved transient response using gain enhanced feed
forward path compensation is presented in this paper. It is based on a
cascade of a voltage amplifier and a transconductor stage in the feed
forward path with regular error amplifier to form a composite gainenhanced
feed forward stage. It broadens the gain bandwidth and thus
improves the transient response without substantial increase in power
consumption. The proposed LDO, designed for a maximum output
current of 100 mA in UMC 180 nm, requires a quiescent current of
69 )A. An undershot of 153.79mV for a load current changes from
0mA to 100mA and an overshoot of 196.24mV for current change of
100mA to 0mA. The settling time is approximately 1.1 )s for the
output voltage undershooting case. The load regulation is of 2.77
)V/mA at load current of 100mA. Reference voltage is generated by
using an accurate band gap reference circuit of 0.8V.The costly
features of SOC such as total chip area and power consumption is
drastically reduced by the use of only a total compensation
capacitance of 6pF while consuming power consumption of 0.096
mW.
", keywords = "Capacitor-less LDO, frequency compensation,
Transient response, latch, self-biased differential amplifier.", volume = "8", number = "10", pages = "1600-5", }
