Abstract: Paper presents a low power, high speed, sense-amplifier based flip-flop (SAFF). The flip-flop’s power con-sumption and delay are greatly reduced by employing a new conditionally precharge sense-amplifier stage and a single-ended latch stage. Glitch-free and contention-free latch operation is achieved by using a conditional cut-off strategy. The design uses fewer transistors, has a lower clock load, and has a simple structure, all of which contribute to a near-zero setup time. When compared to previous flip-flop structures proposed for similar input/output conditions, this design’s performance and overall PDP have improved. The post layout simulation of the circuit uses 2.91µW of power and has a delay of 65.82 ps. Overall, the power-delay product has seen some enhancements. Cadence Virtuoso Designing tool with CMOS 90nm technology are used for all designs.
Abstract: In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.
Abstract: In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.
Abstract: In this paper, we proposed a novel SCR (Silicon Controlled
Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O
and power clamp. The proposed device has a higher holding voltage
characteristic than conventional SCR. These characteristics enable to have
latch-up immunity under normal operating conditions as well as superior full
chip ESD protection. The proposed device was analyzed to figure out
electrical characteristics and tolerance robustness in term of individual
design parameters (D1, D2, D3). They are investigated by using the
Synopsys TCAD simulator. As a result of simulation, holding voltage
increased with different design parameters. The holding voltage of the
proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD
device with the high holding voltage is proposed. In the simulation results,
2-stack has holding voltage of 6.8V and 3-stack has holding voltage of
10.5V. The simulation results show that holding voltage of stacking
structure can be larger than the operation voltage of high-voltage
application.
Abstract: This paper proposed a silicon controller rectifier (SCR)
based ESD protection device to protect low voltage ESD for integrated
circuit. The proposed ESD protection device has low trigger voltage
and high holding voltage compared with conventional SCR-based
ESD protection devices. The proposed ESD protection circuit is
verified and compared by TCAD simulation. This paper verified
effective low voltage ESD characteristics with low trigger voltage of
5.79V and high holding voltage of 3.5V through optimization
depending on design variables (D1, D2, D3 and D4).
Abstract: This paper impart the design and testing of
Nanotechnology based sequential circuits using multiplexer
conservative QCA (MX-CQCA) logic gates, which is easily testable
using only two vectors. This method has great prospective in the
design of sequential circuits based on reversible conservative logic
gates and also smashes the sequential circuits implemented in
traditional gates in terms of testability. Reversible circuits are similar
to usual logic circuits except that they are built from reversible gates.
Designs of multiplexer conservative QCA logic based two vectors
testable double edge triggered (DET) sequential circuits in VHDL
language are also accessible here; it will also diminish intricacy in
testing side. Also other types of sequential circuits such as D, SR, JK
latches are designed using this MX-CQCA logic gate. The objective
behind the proposed design methodologies is to amalgamate
arithmetic and logic functional units optimizing key metrics such as
garbage outputs, delay, area and power. The projected MX-CQCA
gate outshines other reversible gates in terms of the intricacy, delay.
Abstract: Anultra-low power capacitor less low-dropout voltage
regulator with improved transient response using gain enhanced feed
forward path compensation is presented in this paper. It is based on a
cascade of a voltage amplifier and a transconductor stage in the feed
forward path with regular error amplifier to form a composite gainenhanced
feed forward stage. It broadens the gain bandwidth and thus
improves the transient response without substantial increase in power
consumption. The proposed LDO, designed for a maximum output
current of 100 mA in UMC 180 nm, requires a quiescent current of
69 )A. An undershot of 153.79mV for a load current changes from
0mA to 100mA and an overshoot of 196.24mV for current change of
100mA to 0mA. The settling time is approximately 1.1 )s for the
output voltage undershooting case. The load regulation is of 2.77
)V/mA at load current of 100mA. Reference voltage is generated by
using an accurate band gap reference circuit of 0.8V.The costly
features of SOC such as total chip area and power consumption is
drastically reduced by the use of only a total compensation
capacitance of 6pF while consuming power consumption of 0.096
mW.
Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: This paper presents a SCR-based ESD protection devices for I/O clamp and power rail clamp, respectably. These devices have a low trigger voltage and high holding voltage characteristics than conventional SCR device. These devices are fabricated by using 0.35um BCD (Bipolar-CMOS-DMOS) processes. These devices were validated using a TLP system. From the experimental results, the device for I/O ESD clamp has a trigger voltage of 5.8V. Also, the device for power rail ESD clamp has a holding voltage of 7.7V.
Abstract: The use of Quantum dots is a promising emerging
Technology for implementing digital system at the nano level. It is
effecient for attractive features such as faster speed , smaller size and
low power consumption than transistor technology. In this paper,
various Combinational and sequential logical structures - HALF
ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND,
NOR, XOR,XNOR are discussed based on QCA design, with
comparatively less number of cells and area. By applying these
layouts, the hardware requirements for a QCA design can be reduced.
These structures are designed and simulated using QCA Designer
Tool. By taking full advantage of the unique features of this
technology, we are able to create complete circuits on a single layer
of QCA. Such Devices are expected to function with ultra low
power Consumption and very high speeds.
Abstract: This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigma-delta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigma-delta modulator improves the timing
margin about 16%. The sub-circuits of sigma-delta modulator such as
SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and
DWA are designed with the non-ideal characteristics taken into
account. The sigma-delta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.
Abstract: Memristor is also known as the fourth fundamental
passive circuit element. When current flows in one direction through
the device, the electrical resistance increases and when current flows
in the opposite direction, the resistance decreases. When the current
is stopped, the component retains the last resistance that it had, and
when the flow of charge starts again, the resistance of the circuit will
be what it was when it was last active. It behaves as a nonlinear
resistor with memory. Recently memristors have generated wide
research interest and have found many applications. In this paper we
survey the various applications of memristors which include non
volatile memory, nanoelectronic memories, computer logic,
neuromorphic computer architectures low power remote sensing
applications, crossbar latches as transistor replacements, analog
computations and switches.
Abstract: A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.