Abstract: In this paper, we presented the LDO (low-dropout) regulator which enhanced the PSRR by applying the constant current source generation technique through the BGR (Band Gap Reference) to form the noise sensing circuit. The current source through the BGR has a constant current value even if the applied voltage varies. Then, the noise sensing circuit, which is composed of the current source through the BGR, operated between the error amplifier and the pass transistor gate of the LDO regulator. As a result, the LDO regulator has a PSRR of -68.2 dB at 1k Hz, -45.85 dB at 1 MHz and -45 dB at 10 MHz. the other performance of the proposed LDO was maintained at the same level of the conventional LDO regulator.
Abstract: In this paper, a Silicon Controlled Rectifier (SCR)-based Electrostatic Discharge (ESD) protection circuit with high holding voltage and high robustness characteristics is proposed. Unlike conventional SCR, the proposed circuit has low trigger voltage and high holding voltage and provides effective ESD protection with latch-up immunity. In addition, the TCAD simulation results show that the proposed circuit has better electrical characteristics than the conventional SCR. A stack technology was used for voltage-specific applications. Consequentially, the proposed circuit has a trigger voltage of 17.60 V and a holding voltage of 3.64 V.
Abstract: In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.
Abstract: In this paper, we proposed a novel SCR (Silicon Controlled
Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O
and power clamp. The proposed device has a higher holding voltage
characteristic than conventional SCR. These characteristics enable to have
latch-up immunity under normal operating conditions as well as superior full
chip ESD protection. The proposed device was analyzed to figure out
electrical characteristics and tolerance robustness in term of individual
design parameters (D1, D2, D3). They are investigated by using the
Synopsys TCAD simulator. As a result of simulation, holding voltage
increased with different design parameters. The holding voltage of the
proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD
device with the high holding voltage is proposed. In the simulation results,
2-stack has holding voltage of 6.8V and 3-stack has holding voltage of
10.5V. The simulation results show that holding voltage of stacking
structure can be larger than the operation voltage of high-voltage
application.
Abstract: The high efficiency power management IC (PMIC) with switching device is presented in this paper. PMIC is controlled with PFM control method in order to have high power efficiency at high current level. Dynamic Threshold voltage CMOS (DT-CMOS) with low on-resistance is designed to decrease conduction loss. The threshold voltage of DT-CMOS drops as the gate voltage increase, resulting in a much higher current handling capability than standard MOSFET. PFM control circuits consist of a generator, AND gate and comparator. The generator is made to have 1.2MHz oscillation voltage. The DC-DC converter based on PFM control circuit and low on-resistance switching device is presented in this paper.
Abstract: In this paper, a novel LVTSCR-based device for
electrostatic discharge (ESD) protection of integrated circuits (ICs) is
designed, fabricated and characterized. The proposed device is similar
to the conventional LVTSCR but it has an embedded PMOSFET in the
anode n-well to enhance the turn on speed, the clamping capability and
the robustness. This is possible because the embedded PMOSFET
provides the sub-path of ESD discharge current. The TLP, HBM and
MM testing are carried out to verify the ESD performance of the
proposed devices, which are fabricated in 0.35um
(Bipolar-CMOS-DMOS) BCDMOS process. The device has the
robustness of 70mA/um that is higher about 60mA/um than the
LVTSCR, approximately.