Abstract: Digital systems are said to be constructed using basic logic gates. These gates are the NOR, NAND, AND, OR, EXOR & EXNOR gates. This paper presents a robust three transistors (3T) based NAND and NOR gates with precise output logic levels, yet maintaining equivalent performance than the existing logic structures. This new set of 3T logic gates are based on CMOS inverter and Pass Transistor Logic (PTL). The new universal logic gates are characterized by better speed and lower power dissipation which can be straightforwardly fabricated as memory ICs for high performance computer networks. The simulation tests were performed using standard BPTM 22nm process technology using SYNOPSYS HSPICE. The 3T NAND gate is evaluated using C17 benchmark circuit and 3T NOR is gate evaluated using a D-Latch. According to HSPICE simulation in 22 nm CMOS BPTM process technology under given conditions and at room temperature, the proposed 3T gates shows an improvement of 88% less power consumption on an average over conventional CMOS logic gates. The devices designed with 3T gates will make longer battery life by ensuring extremely low power consumption.
Abstract: Analysis of blood vessel mechanics in normal and
diseased conditions is essential for disease research, medical device
design and treatment planning. In this work, 3D finite element
models of normal vessel and atherosclerotic vessel with 50% plaque
deposition were developed. The developed models were meshed
using finite number of tetrahedral elements. The developed models
were simulated using actual blood pressure signals. Based on the
transient analysis performed on the developed models, the parameters
such as total displacement, strain energy density and entropy per unit
volume were obtained. Further, the obtained parameters were used to
develop artificial neural network models for analyzing normal and
atherosclerotic blood vessels. In this paper, the objectives of the
study, methodology and significant observations are presented.