Abstract: This paper presents a method of reducing the feedback
delay time of DWA(Data Weighted Averaging) used in sigma-delta
modulators. The delay time reduction results from the elimination of
the latch at the quantizer output and also from the falling edge
operation. The designed sigma-delta modulator improves the timing
margin about 16%. The sub-circuits of sigma-delta modulator such as
SC(Switched Capacitor) integrator, 9-level quantizer, comparator, and
DWA are designed with the non-ideal characteristics taken into
account. The sigma-delta modulator has a maximum SNR (Signal to
Noise Ratio) of 84 dB or 13 bit resolution.
Abstract: A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.