High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications
A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.
[1] Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama,
Steve Kosic, jun Cao and Shu-Lap Chan, " A 90-dB SNR 2.5-MHz
Output-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at
8X Oversampling Ratio", IEEE Journal of Solid-State Circuits, ,vol.35,
No 12, December 2000.W
[2] Todd L.Brooks, D.H Robertson, D.F Kelly, A.Del Muro and
S.W.Harston, "A cascade Sigma-Delta Pipeline A/D Converter with 1.25
MHz Signal Bandwidth and 89 dB SNR", IEEE Journal of Solid-
Circuits, Vol 32, No.12, December 1997.
[3] Matthew R.Miller and Craig S.Petrie, "A multibit Sigma-Delta ADC for
Multimode Receivers", IEEE Journal of Solid- Circuits, Vol 38, No. 3,
March 2003.
[4] Yong-In Park, S.Karthikeyan, Wern Ming Koe, Zhongnong Jiang and
Tiak-Chean Tan, « A 16-Bit, 5 MHz Multi-Bit Sigma-Delta ADC Using
Adaptively Randomized DWA», IEEE Custom Integrated circuits
conference, 2003.
[5] K.Vleugels, S.Rabii and Bruce A.Wooley, "A 2.5-V Sigma-Delta
Modulator for Broadband Communications Applications", IEEE Journal
of Solid- Circuits, Vol 36, No.12, December 2001.
[6] F. Medeiro, B. Perez-Verdu and A. Rodriguez-Vazquez, "A 13-Bit, 2.2-
MS/s, 55-mW Multibit Cascade ΣΔ Modulator in CMOS 0.7-╬╝m Single-
Poly Technology", IEEE Journal of Solid-State Circuits, Vol 34, No.6,
June1999.
[7] A.R.Feldman, B.E.Boser and P.R.Gray, "A 13-Bit, 1.4-MS/s Sigma-
Delta Modulator for RF Baseband Channel Applications", IEEE Journal
of Solid- Circuits, Vol 33, No.10, October 1998.
[8] B. Limketkai and B. Victor, "The Design of A High-Bandwidth Sigma-
Delta Modulator", EECS 247 Project report December 2000.
[9] H.Lampinen and O.Vainio, "Low-Voltage fourth-order CMOS sigmadelta
modulator implementation", Electronics Letters, Vol.37 No12, 7th
June 2001.
[10] S.Yan and E.Sanchez-Sinencio, "A Continuous-Time ΣΔ Modulator
with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth", IEEE
Journal of Solid- Circuits, Vol 39, No. 1, January 2004.
[11] R. Del Rio, J.M de la Rosa, B. Perez-Verdu, M. Delgado-Restituto, R.
Dominguez-Castro, F. Medeiro and A. Rodriguez-Vazquez, "Highly
Linear 2.5-V CMOS ´ÇáModulator for ADSL+", IEEE Transactions On
Circuits and Systems-I: Regular Papers, Vol.51, No 1, January 2004.
[12] Yves Geerts, Michiel Steyaert and Willy Sansen, "Design of Multi-Bit
ΣΔ A/D Converters", Kluwer Academic Publishers, Boston, 2002.
[13] S. R. Norswortthy, R. Schreier, and G. C. Temes, Eds "Delta-Sigma-
Data Converters: Theory, Design, and Simulation", New York: IEEE
Press, 1997.
[14] Rex T.Baird and Terri S.Fiez, "Linearity Enhancement of Multibit ΣΔ
A/D and D/A Converters Using Data Weighted Averaging", IEEE
Transactions On Circuits and Systems-II: Analog and Digital Signal
Processing, Vol.42, No12, December 1995.
[15] F. T. Braz, P. Loumeau, R. C. S. Freire, E. de Lira Mendes, "Data
Weighted Averaging Technique in Multibit Sigma-Delta Modulators",
Midwest Symposium on Circuits and Systems, USA, August 1998.
[16] H. Daoud, S. Ben Salem, S. Zouari, and M Loulou, "Folded Cascode
OTA Design for Wide Band Application", IEEE International
Conference on Design &Test of Integrated Systems DTIS, Septembre
2006.
[17] P. Malcovati, et al, "Behavioural modelling of switched-capacitor sigma
delta modulators", in IEEE trans. Circuits syst. II, vol.50, n┬░.3,2003, pp.
352-364.
[18] E. Foglemen, I. Galton, W. Huff, and H. Jensen, "A 3.3 V single-poly
CMOS audio ADC delta sigma modulator with 98 dB peak SINAD," in
Proc. IEEE 1999 CICC, May 1999, pp. 7. 4. 1-4.
[1] Ichiro Fujimori, Lorenzo Longo, Armond Hairapetian, Kazushi Seiyama,
Steve Kosic, jun Cao and Shu-Lap Chan, " A 90-dB SNR 2.5-MHz
Output-Rate ADC Using Cascaded Multibit Delta-Sigma Modulation at
8X Oversampling Ratio", IEEE Journal of Solid-State Circuits, ,vol.35,
No 12, December 2000.W
[2] Todd L.Brooks, D.H Robertson, D.F Kelly, A.Del Muro and
S.W.Harston, "A cascade Sigma-Delta Pipeline A/D Converter with 1.25
MHz Signal Bandwidth and 89 dB SNR", IEEE Journal of Solid-
Circuits, Vol 32, No.12, December 1997.
[3] Matthew R.Miller and Craig S.Petrie, "A multibit Sigma-Delta ADC for
Multimode Receivers", IEEE Journal of Solid- Circuits, Vol 38, No. 3,
March 2003.
[4] Yong-In Park, S.Karthikeyan, Wern Ming Koe, Zhongnong Jiang and
Tiak-Chean Tan, « A 16-Bit, 5 MHz Multi-Bit Sigma-Delta ADC Using
Adaptively Randomized DWA», IEEE Custom Integrated circuits
conference, 2003.
[5] K.Vleugels, S.Rabii and Bruce A.Wooley, "A 2.5-V Sigma-Delta
Modulator for Broadband Communications Applications", IEEE Journal
of Solid- Circuits, Vol 36, No.12, December 2001.
[6] F. Medeiro, B. Perez-Verdu and A. Rodriguez-Vazquez, "A 13-Bit, 2.2-
MS/s, 55-mW Multibit Cascade ΣΔ Modulator in CMOS 0.7-╬╝m Single-
Poly Technology", IEEE Journal of Solid-State Circuits, Vol 34, No.6,
June1999.
[7] A.R.Feldman, B.E.Boser and P.R.Gray, "A 13-Bit, 1.4-MS/s Sigma-
Delta Modulator for RF Baseband Channel Applications", IEEE Journal
of Solid- Circuits, Vol 33, No.10, October 1998.
[8] B. Limketkai and B. Victor, "The Design of A High-Bandwidth Sigma-
Delta Modulator", EECS 247 Project report December 2000.
[9] H.Lampinen and O.Vainio, "Low-Voltage fourth-order CMOS sigmadelta
modulator implementation", Electronics Letters, Vol.37 No12, 7th
June 2001.
[10] S.Yan and E.Sanchez-Sinencio, "A Continuous-Time ΣΔ Modulator
with 88-dB Dynamic Range and 1.1-MHz Signal Bandwidth", IEEE
Journal of Solid- Circuits, Vol 39, No. 1, January 2004.
[11] R. Del Rio, J.M de la Rosa, B. Perez-Verdu, M. Delgado-Restituto, R.
Dominguez-Castro, F. Medeiro and A. Rodriguez-Vazquez, "Highly
Linear 2.5-V CMOS ´ÇáModulator for ADSL+", IEEE Transactions On
Circuits and Systems-I: Regular Papers, Vol.51, No 1, January 2004.
[12] Yves Geerts, Michiel Steyaert and Willy Sansen, "Design of Multi-Bit
ΣΔ A/D Converters", Kluwer Academic Publishers, Boston, 2002.
[13] S. R. Norswortthy, R. Schreier, and G. C. Temes, Eds "Delta-Sigma-
Data Converters: Theory, Design, and Simulation", New York: IEEE
Press, 1997.
[14] Rex T.Baird and Terri S.Fiez, "Linearity Enhancement of Multibit ΣΔ
A/D and D/A Converters Using Data Weighted Averaging", IEEE
Transactions On Circuits and Systems-II: Analog and Digital Signal
Processing, Vol.42, No12, December 1995.
[15] F. T. Braz, P. Loumeau, R. C. S. Freire, E. de Lira Mendes, "Data
Weighted Averaging Technique in Multibit Sigma-Delta Modulators",
Midwest Symposium on Circuits and Systems, USA, August 1998.
[16] H. Daoud, S. Ben Salem, S. Zouari, and M Loulou, "Folded Cascode
OTA Design for Wide Band Application", IEEE International
Conference on Design &Test of Integrated Systems DTIS, Septembre
2006.
[17] P. Malcovati, et al, "Behavioural modelling of switched-capacitor sigma
delta modulators", in IEEE trans. Circuits syst. II, vol.50, n┬░.3,2003, pp.
352-364.
[18] E. Foglemen, I. Galton, W. Huff, and H. Jensen, "A 3.3 V single-poly
CMOS audio ADC delta sigma modulator with 98 dB peak SINAD," in
Proc. IEEE 1999 CICC, May 1999, pp. 7. 4. 1-4.
@article{"International Journal of Electrical, Electronic and Communication Sciences:54379", author = "S. Zouari and H. Daoud and M. Loulou and P. Loumeau and N. Masmoudi", title = "High Order Cascade Multibit ΣΔ Modulator for Wide Bandwidth Applications", abstract = "A wideband 2-1-1 cascaded ΣΔ modulator with a
single-bit quantizer in the two first stages and a 4-bit quantizer in the
final stage is developed. To reduce sensitivity of digital-to-analog
converter (DAC) nonlinearities in the feedback of the last stage,
dynamic element matching (DEM) is introduced. This paper presents
two modelling approaches: The first is MATLAB description and the
second is VHDL-AMS modelling of the proposed architecture and
exposes some high-level-simulation results allowing a behavioural
study. The detail of both ideal and non-ideal behaviour modelling are
presented. Then, the study of the effect of building blocks
nonidealities is presented; especially the influences of nonlinearity,
finite operational amplifier gain, amplifier slew rate limitation and
capacitor mismatch. A VHDL-AMS description presents a good
solution to predict system-s performances and can provide sensitivity
curves giving the impact of nonidealities on the system performance.", keywords = "behavioural study, DAC nonlinearity, DEM, ΣΔ
modulator, VHDL-AMS modelling.", volume = "1", number = "9", pages = "1301-7", }
