A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage
In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.
[1] Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed. Springer, US, 2002.
[2] M.D. Ker and C.C. Yen “investigation and Design of on-Chip Power-Rail ESD Clamp Circuits without Suffering Latch up-Like Failure during System-Level ESD Test” IEEE J, Solid-State Circuit, vol. 43, no. 11, pp.2533-2545, 2008.
[3] V. Vashchenko, A. Sinkevitch, V.F., “Physical Limitaions of Semiconductor Devices, Springer, p.340, 2008
[4] Yong Seo Koo, et. al., “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.
[5] Sheng-Lyang Jang, et. al., “Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,” Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.
[6] P.-Y Ran, M. Indrajjit, P.-H. Li and S. H. Voldman. “RC-triggered PNP and NPN Simultaneously Switched Silicon Controlled Rectrifier ESD Networks for Sub-0.18um Technology” in proc. Of IEEE int. symp. On physical and failure Analysis of Intergrated Circuits, pp. 71-75, 2005
[7] W.Y Chen, et. al., “Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,” device and system, APCCAS 2008, pp. 61-64, 2008.
[8] J. Y. Lee "Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time," j.inst.Korean.electr.electron.eng, vol. 20, no. 3, pp. 295-398, 2016.
[9] O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," EOS/ESD Symp, pp. 77-86, 2006.
[10] K. D Kim "A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication," j.inst.Korean.electr.electron.eng, vol. 9, no. 2, pp. 83-91, 2005.
[11] M. D. Ker and H. H. Chang, “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” J. Electro- statics, vol. 47, pp.215-248, 1999.
[12] Y. Koo, K. Lee, K. Kim, and J. Kwon, “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.
[13] S.-L. Jang, L.-S. Lin, and S.-H. Li, “Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,” Solid-State Electronics, vol. 45, pp. 2005-2009, 2001.
[14] V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 2, pp. 273-280, 2004.
[1] Albert Z, H. Wang, On-Chip ESD Protection for Integrated devices 2nd ed. Springer, US, 2002.
[2] M.D. Ker and C.C. Yen “investigation and Design of on-Chip Power-Rail ESD Clamp Circuits without Suffering Latch up-Like Failure during System-Level ESD Test” IEEE J, Solid-State Circuit, vol. 43, no. 11, pp.2533-2545, 2008.
[3] V. Vashchenko, A. Sinkevitch, V.F., “Physical Limitaions of Semiconductor Devices, Springer, p.340, 2008
[4] Yong Seo Koo, et. al., “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, Vol. 40, pp. 1007-1012, 2009.
[5] Sheng-Lyang Jang, et. al., “Temperature-dependent dynamic triggering characteristics of SCR-type ESD protection devices,” Solid-State Electronics, Vol.45, pp. 2005-2009, 2001.
[6] P.-Y Ran, M. Indrajjit, P.-H. Li and S. H. Voldman. “RC-triggered PNP and NPN Simultaneously Switched Silicon Controlled Rectrifier ESD Networks for Sub-0.18um Technology” in proc. Of IEEE int. symp. On physical and failure Analysis of Intergrated Circuits, pp. 71-75, 2005
[7] W.Y Chen, et. al., “Measurement on Snapback Holding voltage of High-Voltage LDMOS for Latch-up Consideration,” device and system, APCCAS 2008, pp. 61-64, 2008.
[8] J. Y. Lee "Analysis of SCR, MVSCR, LVTSCR With I-V Characteristic and Turn-On-Time," j.inst.Korean.electr.electron.eng, vol. 20, no. 3, pp. 295-398, 2016.
[9] O. Quittard, Z. Mrcarica, F. Blanc, G. Notermans, T. Smedes, and H.van Zwol, "ESD protection for high-voltage CMOS technologies," EOS/ESD Symp, pp. 77-86, 2006.
[10] K. D Kim "A Study on the Novel SCR Nano ESD Protection Device Design and Fabrication," j.inst.Korean.electr.electron.eng, vol. 9, no. 2, pp. 83-91, 2005.
[11] M. D. Ker and H. H. Chang, “How to safely apply the LVTSCR for CMOS whole-chip ESD protection without being accidentally triggered on,” J. Electro- statics, vol. 47, pp.215-248, 1999.
[12] Y. Koo, K. Lee, K. Kim, and J. Kwon, “Design of SCR-based ESD protection device for power clamp using deep-submicron CMOS technology,” Microelectronics Journal, vol. 40, pp. 1007-1012, 2009.
[13] S.-L. Jang, L.-S. Lin, and S.-H. Li, “Temperature-dependent dynamic trig-gering characteristics of SCR-type ESD protection circuits,” Solid-State Electronics, vol. 45, pp. 2005-2009, 2001.
[14] V. A. Vashchenko, A. Concannon, M. ter Beek, and P. Hopper "High Holding Voltage Cascoded LVTSCR Structures for 5.5-V Tolerant ESD Protection Clamps," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 2, pp. 273-280, 2004.
@article{"International Journal of Electrical, Electronic and Communication Sciences:76752", author = "Hee-Guk Chae and Bo-Bae Song and Kyoung-Il Do and Jeong-Yun Seo and Yong-Seo Koo", title = "A Study on ESD Protection Circuit Applying Silicon Controlled Rectifier-Based Stack Technology with High Holding Voltage", abstract = "In this study, an improved Electrostatic Discharge (ESD) protection circuit with low trigger voltage and high holding voltage is proposed. ESD has become a serious problem in the semiconductor process because the semiconductor density has become very high these days. Therefore, much research has been done to prevent ESD. The proposed circuit is a stacked structure of the new unit structure combined by the Zener Triggering (SCR ZTSCR) and the High Holding Voltage SCR (HHVSCR). The simulation results show that the proposed circuit has low trigger voltage and high holding voltage. And the stack technology is applied to adjust the various operating voltage. As the results, the holding voltage is 7.7 V for 2-stack and 10.7 V for 3-stack.", keywords = "ESD, SCR, latch-up, power clamp, holding voltage.", volume = "11", number = "12", pages = "1219-4", }
