Abstract: This paper proposed high level feature for online Lao handwritten recognition. This feature must be high level enough so that the feature is not change when characters are written by different persons at different speed and different proportion (shorter or longer stroke, head, tail, loop, curve). In this high level feature, a character is divided in to sequence of curve segments where a segment start where curve reverse rotation (counter clockwise and clockwise). In each segment, following features are gathered cumulative change in direction of curve (- for clockwise), cumulative curve length, cumulative length of left to right, right to left, top to bottom and bottom to top ( cumulative change in X and Y axis of segment). This feature is simple yet robust for high accuracy recognition. The feature can be gather from parsing the original time sampling sequence X, Y point of the pen location without re-sampling. We also experiment on other segmentation point such as the maximum curvature point which was widely used by other researcher. Experiments results show that the recognition rates are at 94.62% in comparing to using maximum curvature point 75.07%. This is due to a lot of variations of turning points in handwritten.
Abstract: The general purpose processors that are used in
embedded systems must support constraints like execution time,
power consumption, code size and so on. On the other hand an
Application Specific Instruction-set Processor (ASIP) has advantages
in terms of power consumption, performance and flexibility. In this
paper, a 16-bit Application Specific Instruction-set processor for the
sensor data transfer is proposed. The designed processor architecture
consists of on-chip transmitter and receiver modules along with the
processing and controlling units to enable the data transmission and
reception on a single die. The data transfer is accomplished with less
number of instructions as compared with the general purpose
processor. The ASIP core operates at a maximum clock frequency of
1.132GHz with a delay of 0.883ns and consumes 569.63mW power
at an operating voltage of 1.2V. The ASIP is implemented in Verilog
HDL using the Xilinx platform on Virtex4.
Abstract: This paper study the high-level modelling and design
of delta-sigma (ΔΣ) noise shapers for audio Digital-to-Analog
Converter (DAC) so as to eliminate the in-band Signal-to-Noise-
Ratio (SNR) degradation that accompany one channel mismatch in
audio signal. The converter combines a cascaded digital signal
interpolation, a noise-shaping single loop delta-sigma modulator with
a 5-bit quantizer resolution in the final stage. To reduce sensitivity of
Digital-to-Analog Converter (DAC) nonlinearities of the last stage, a
high pass second order Data Weighted Averaging (R2DWA) is
introduced. This paper presents a MATLAB description modelling
approach of the proposed DAC architecture with low distortion and
swing suppression integrator designs. The ΔΣ Modulator design can
be configured as a 3rd-order and allows 24-bit PCM at sampling rate
of 64 kHz for Digital Video Disc (DVD) audio application. The
modeling approach provides 139.38 dB of dynamic range for a 32
kHz signal band at -1.6 dBFS input signal level.
Abstract: Phase locked loops in 10 Gb/s and faster data links are
low phase noise devices. Characterization of their phase jitter
transfer functions is difficult because the intrinsic noise of the PLLs
is comparable to the phase noise of the reference clock signal. The
problem is solved by using a linear model to account for the intrinsic
noise. This study also introduces a novel technique for measuring the
transfer function. It involves the use of the reference clock as a
source of wideband excitation, in contrast to the commonly used
sinusoidal excitations at discrete frequencies. The data reported here
include the intrinsic noise of a PLL for 10 Gb/s links and the jitter
transfer function of a PLL for 12.8 Gb/s links. The measured transfer
function suggests that the PLL responded like a second order linear
system to a low noise reference clock.
Abstract: The use of Quantum dots is a promising emerging
Technology for implementing digital system at the nano level. It is
effecient for attractive features such as faster speed , smaller size and
low power consumption than transistor technology. In this paper,
various Combinational and sequential logical structures - HALF
ADDER, SR Latch and Flip-Flop, D Flip-Flop preceding NAND,
NOR, XOR,XNOR are discussed based on QCA design, with
comparatively less number of cells and area. By applying these
layouts, the hardware requirements for a QCA design can be reduced.
These structures are designed and simulated using QCA Designer
Tool. By taking full advantage of the unique features of this
technology, we are able to create complete circuits on a single layer
of QCA. Such Devices are expected to function with ultra low
power Consumption and very high speeds.
Abstract: Time interleaved sigma-delta (TIΣΔ) architecture is a
potential candidate for high bandwidth analog to digital converters
(ADC) which remains a bottleneck for software and cognitive radio
receivers. However, the performance of the TIΣΔ architecture is
limited by the unavoidable gain and offset mismatches resulting
from the manufacturing process. This paper presents a novel digital
calibration method to compensate the gain and offset mismatch
effect. The proposed method takes advantage of the reconstruction
digital signal processing on each channel and requires only few logic
components for implementation. The run time calibration is estimated
to 10 and 15 clock cycles for offset cancellation and gain mismatch
calibration respectively.
Abstract: This paper describes a 2.4 GHz passive switch mixer
and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO)
with an inversion-mode MOS varactor. Both circuits are implemented
using a 1P8M 0.13 μm process. The switch mixer has an input
referred 1 dB compression point of -3.89 dBm and a conversion
gain of -0.96 dB when the local oscillator power is +2.5 dBm.
The VCO consumes only 1.75 mW, while drawing 1.45 mA from a
1.2 V supply voltage. In order to reduce the passives size, the VCO
natural oscillation frequency is 5 GHz. A clocked CMOS divideby-
two circuit is used for frequency division and quadrature phase
generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz
frequency offset and a 2.35-2.5 GHz tuning range (after the frequency
division), thus complying with ZigBee requirements.
Abstract: A new mechanism responsible for structural life
consumption due to resonant fatigue in turbine blades, or vanes, is
presented and explained. A rotating blade or vane in a gas turbine can
change its contour due to erosion and/or material build up, in any of
these instances, the surface pressure distribution occurring on the
suction and pressure sides of blades-vanes can suffer substantial
modification of their pressure and temperatures envelopes and flow
characteristics. Meanwhile, the relative rotation between the blade
and duct vane while the pressurized gas flows and the consequent
wake crossings, will induce a fluctuating thrust force or lift that will
excite the blade.
An actual totally used up set of vane-blade components in a HP
turbine power stage in a gas turbine is analyzed. The blade suffered
some material erosion mostly at the trailing edge provoking a
peculiar surface pressure envelope which evolved as the relative
position between the vane and the blade passed in front of each other.
Interestingly preliminary modal analysis for this eroded blade
indicates several natural frequencies within the aeromechanic power
spectrum, moreover, the highest frequency component is 94% of one
natural frequency indicating near resonant condition.
Independently of other simultaneously occurring fatigue cycles
(such as thermal, centrifugal stresses).
Abstract: Reversible logic is becoming more and more prominent
as the technology sets higher demands on heat, power, scaling
and stability. Reversible gates are able at any time to "undo" the
current step or function. Multiple-valued logic has the advantage of
transporting and evaluating higher bits each clock cycle than binary.
Moreover, we demonstrate in this paper, combining these disciplines
we can construct powerful multiple-valued reversible logic structures.
In this paper a reversible block implemented by pseudo floatinggate
can perform AD-function and a DA-function as its reverse
application.
Abstract: We have fabricated a-IGZO TFT and investigated the
stability under positive DC and AC bias stress. The threshold voltage
of a-IGZO TFT shifts positively under those biases, and that reduces
on-current. For this reason, conventional shift-register circuit
employing TFTs which stressed by positive bias will be unstable, may
do not work properly. We have designed a new 6-transistor
shift-register, which has less transistors than prior circuits. The TFTs
of the proposed shift-register are not suffering from positive DC or AC
stress, mainly kept unbiased. Despite the compact design, the stable
output signal was verified through the SPICE simulation even under
RC delay of clock signal.
Abstract: In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: This paper presents design trade-off and performance impacts of
the amount of pipeline phase of control path signals in a wormhole-switched
network-on-chip (NoC). The numbers of the pipeline phase of the control
path vary between two- and one-cycle pipeline phase. The control paths
consist of the routing request paths for output selection and the arbitration
paths for input selection. Data communications between on-chip routers are
implemented synchronously and for quality of service, the inter-router data
transports are controlled by using a link-level congestion control to avoid
lose of data because of an overflow. The trade-off between the area (logic
cell area) and the performance (bandwidth gain) of two proposed NoC router
microarchitectures are presented in this paper. The performance evaluation is
made by using a traffic scenario with different number of workloads under
2D mesh NoC topology using a static routing algorithm. By using a 130-nm
CMOS standard-cell technology, our NoC routers can be clocked at 1 GHz,
resulting in a high speed network link and high router bandwidth capacity
of about 320 Gbit/s. Based on our experiments, the amount of control path
pipeline stages gives more significant impact on the NoC performance than
the impact on the logic area of the NoC router.
Abstract: The trend of growing density on chips has increases not
only the temperature in chips but also the gradient of the temperature
depending on locations. In this paper, we propose the balanced skew
tree generation technique for minimizing the clock skew that is
affected by the temperature gradients on chips. We calculate the
interconnect delay using Elmore delay equation, and find out the
optimal balanced clock tree by modifying the clock trees generated
through the Deferred Merge Embedding(DME) algorithm. The
experimental results show that the distance variance of clock insertion
points with and without considering the temperature gradient can be
lowered below 54% and we confirm that the skew is remarkably
decreased after applying the proposed technique.
Abstract: Global Positioning System (GPS) technology is widely used today in the areas of geodesy and topography as well as in aeronautics mainly for military purposes. Due to the military usage of GPS, full access and use of this technology is being denied to the civilian user who must then work with a less accurate version. In this paper we focus on the estimation of the receiver coordinates ( X, Y, Z ) and its clock bias ( δtr ) of a fixed point based on pseudorange measurements of a single GPS receiver. Utilizing the instantaneous coordinates of just 4 satellites and their clock offsets, by taking into account the atmospheric delays, we are able to derive a set of pseudorange equations. The estimation of the four unknowns ( X, Y, Z , δtr ) is achieved by introducing an extended Kalman filter that processes, off-line, all the data collected from the receiver. Higher performance of position accuracy is attained by appropriate tuning of the filter noise parameters and by including other forms of biases.
Abstract: The purpose of this research is to develop and apply the
RSCMAC to enhance the dynamic accuracy of Global Positioning
System (GPS). GPS devices provide services of accurate positioning,
speed detection and highly precise time standard for over 98% area on
the earth. The overall operation of Global Positioning System includes
24 GPS satellites in space; signal transmission that includes 2
frequency carrier waves (Link 1 and Link 2) and 2 sets random
telegraphic codes (C/A code and P code), on-earth monitoring stations
or client GPS receivers. Only 4 satellites utilization, the client position
and its elevation can be detected rapidly. The more receivable
satellites, the more accurate position can be decoded. Currently, the
standard positioning accuracy of the simplified GPS receiver is greatly
increased, but due to affected by the error of satellite clock, the
troposphere delay and the ionosphere delay, current measurement
accuracy is in the level of 5~15m. In increasing the dynamic GPS
positioning accuracy, most researchers mainly use inertial navigation
system (INS) and installation of other sensors or maps for the
assistance. This research utilizes the RSCMAC advantages of fast
learning, learning convergence assurance, solving capability of
time-related dynamic system problems with the static positioning
calibration structure to improve and increase the GPS dynamic
accuracy. The increasing of GPS dynamic positioning accuracy can be
achieved by using RSCMAC system with GPS receivers collecting
dynamic error data for the error prediction and follows by using the
predicted error to correct the GPS dynamic positioning data. The
ultimate purpose of this research is to improve the dynamic positioning
error of cheap GPS receivers and the economic benefits will be
enhanced while the accuracy is increased.
Abstract: In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.
Abstract: We developed a new method based on quasimolecular
modeling to simulate the cavity flow in three cavity
shapes: rectangular, half-circular and bucket beer in cgs units. Each
quasi-molecule was a group of particles that interacted in a fashion
entirely analogous to classical Newtonian molecular interactions.
When a cavity flow was simulated, the instantaneous velocity vector
fields were obtained by using an inverse distance weighted
interpolation method. In all three cavity shapes, fluid motion was
rotated counter-clockwise. The velocity vector fields of the three
cavity shapes showed a primary vortex located near the upstream
corners at time t ~ 0.500 s, t ~ 0.450 s and t ~ 0.350 s, respectively.
The configurational kinetic energy of the cavities increased as time
increased until the kinetic energy reached a maximum at time t ~
0.02 s and, then, the kinetic energy decreased as time increased. The
rectangular cavity system showed the lowest kinetic energy, while
the half-circular cavity system showed the highest kinetic energy.
The kinetic energy of rectangular, beer bucket and half-circular
cavities fluctuated about stable average values 35.62 x 103, 38.04 x
103 and 40.80 x 103 ergs/particle, respectively. This indicated that the
half-circular shapes were the most suitable shape for a shrimp pond
because the water in shrimp pond flows best when we compared with
rectangular and beer bucket shape.
Abstract: The nature of wireless ad hoc and sensor networks
make them very attractive to attackers. One of the most popular and
serious attacks in wireless ad hoc networks is wormhole attack and
most proposed protocols to defend against this attack used
positioning devices, synchronized clocks, or directional antennas.
This paper analyzes the nature of wormhole attack and existing
methods of defending mechanism and then proposes round trip time
(RTT) and neighbor numbers based wormhole detection mechanism.
The consideration of proposed mechanism is the RTT between two
successive nodes and those nodes- neighbor number which is needed
to compare those values of other successive nodes. The identification
of wormhole attacks is based on the two faces. The first consideration
is that the transmission time between two wormhole attack affected
nodes is considerable higher than that between two normal neighbor
nodes. The second detection mechanism is based on the fact that by
introducing new links into the network, the adversary increases the
number of neighbors of the nodes within its radius. This system does
not require any specific hardware, has good performance and little
overhead and also does not consume extra energy. The proposed
system is designed in ad hoc on-demand distance vector (AODV)
routing protocol and analysis and simulations of the proposed system
are performed in network simulator (ns-2).