A Novel Implementation of Application Specific Instruction-set Processor (ASIP) using Verilog
The general purpose processors that are used in
embedded systems must support constraints like execution time,
power consumption, code size and so on. On the other hand an
Application Specific Instruction-set Processor (ASIP) has advantages
in terms of power consumption, performance and flexibility. In this
paper, a 16-bit Application Specific Instruction-set processor for the
sensor data transfer is proposed. The designed processor architecture
consists of on-chip transmitter and receiver modules along with the
processing and controlling units to enable the data transmission and
reception on a single die. The data transfer is accomplished with less
number of instructions as compared with the general purpose
processor. The ASIP core operates at a maximum clock frequency of
1.132GHz with a delay of 0.883ns and consumes 569.63mW power
at an operating voltage of 1.2V. The ASIP is implemented in Verilog
HDL using the Xilinx platform on Virtex4.
[1] ARINC Digital Data System Compendium, ARINC Report 419-
3,November 5, 1984.
[2] ARINC Specification 429P1-15, Sep. 1, 1995.
[3] ARINC Specification 429P2-15, March 6, 1996.
[4] "ARINC 629 P1-4 Multi-Transmitter Data Bus","Part1, Technical
Description", December 1995.
[5] ARINC Airborne Computer Data Loader,ARINC Report 615-2, June 1,
1991.
[6] Baburao.K, Apparao.T, Prabu.A.V, RamBabu.E, "VHDL
Implementation and Verification of ARINC-429 Core",International
Journal of engineering, technology and science,vol . 2,2011,pp 174-178.
[7] Jin Soo Kim Sunwoo, Myung H. Sunwoo, "Three low power ASIP
processor designs for communications, video, and audio applications",
International Conference on Design & Technology of Integrated
Systems in Nanoscale Era, 2007. DTIS , pp. 241-244.
[8] Kamaraju.M, Tilak.A.V.N, Lalkishore.K, Baburao.K, "VHDL
implementation and verification of ARINC-429 core", CoRR
International Journal, vol.1,2010,pp1-5.
[9] Kane.G., and Heinrich.J,MIPS RISC Architecture: reference for the
R2000, R3000, R6000 and the new R4000 instruction set computer
architecture. Prentice-Hall, EnglewoodCliffs, NJ, 1992.
[10] Krall.A. "An extended Prolog instruction set for RISC processors", in
VLSI for Artificial Intelligence and Neural Networks (New York, NY,
1991), J. G. Delgado-Frias and W. R. Moore, Eds., Plenum Press, pp.
101-108.
[11] Mohan.R, Land.I, "Building Integrated ARINC 429 Interfaces using an
FPGA". Actel Corporation, Mountain View, California,2005.
[12] Motorola Inc.,"M68000 8-/16-/32-Bit Microprocessors User-s
Manual,"[Onlinedocument],1993(Ninth Edition), available at
http://www.freescale.com/files/32bit/doc/ref_manual/MC68000UM.pdf.
[13] Rose.J, GamaL.A.E, and A. Sangiovanni Vincentelli.A, "Architecture of
Field-Programmable Gate Arrays," Proc. IEEE, vol. 81, no. 7, July
1993, pp.1013-102.
[14] Sato.J, Alomary,A. Y., Honma,Y., Nakata, T., Shiomi, A., Hikichi, N.,
and Imai, M. PEAS-I: "A hardware/software codesign system for ASIP
development", IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Science E77-A, 3 (March 1994),pp
483-491.
[15] Van prate.J, Goossens.G, Lanneer.D, and De man.H " Instruction set
definition and instruction set selection for ASIPs", In Proc. of the 7th
International Symposium on High-Level Synthesis 1994, pp. 11-16.
[1] ARINC Digital Data System Compendium, ARINC Report 419-
3,November 5, 1984.
[2] ARINC Specification 429P1-15, Sep. 1, 1995.
[3] ARINC Specification 429P2-15, March 6, 1996.
[4] "ARINC 629 P1-4 Multi-Transmitter Data Bus","Part1, Technical
Description", December 1995.
[5] ARINC Airborne Computer Data Loader,ARINC Report 615-2, June 1,
1991.
[6] Baburao.K, Apparao.T, Prabu.A.V, RamBabu.E, "VHDL
Implementation and Verification of ARINC-429 Core",International
Journal of engineering, technology and science,vol . 2,2011,pp 174-178.
[7] Jin Soo Kim Sunwoo, Myung H. Sunwoo, "Three low power ASIP
processor designs for communications, video, and audio applications",
International Conference on Design & Technology of Integrated
Systems in Nanoscale Era, 2007. DTIS , pp. 241-244.
[8] Kamaraju.M, Tilak.A.V.N, Lalkishore.K, Baburao.K, "VHDL
implementation and verification of ARINC-429 core", CoRR
International Journal, vol.1,2010,pp1-5.
[9] Kane.G., and Heinrich.J,MIPS RISC Architecture: reference for the
R2000, R3000, R6000 and the new R4000 instruction set computer
architecture. Prentice-Hall, EnglewoodCliffs, NJ, 1992.
[10] Krall.A. "An extended Prolog instruction set for RISC processors", in
VLSI for Artificial Intelligence and Neural Networks (New York, NY,
1991), J. G. Delgado-Frias and W. R. Moore, Eds., Plenum Press, pp.
101-108.
[11] Mohan.R, Land.I, "Building Integrated ARINC 429 Interfaces using an
FPGA". Actel Corporation, Mountain View, California,2005.
[12] Motorola Inc.,"M68000 8-/16-/32-Bit Microprocessors User-s
Manual,"[Onlinedocument],1993(Ninth Edition), available at
http://www.freescale.com/files/32bit/doc/ref_manual/MC68000UM.pdf.
[13] Rose.J, GamaL.A.E, and A. Sangiovanni Vincentelli.A, "Architecture of
Field-Programmable Gate Arrays," Proc. IEEE, vol. 81, no. 7, July
1993, pp.1013-102.
[14] Sato.J, Alomary,A. Y., Honma,Y., Nakata, T., Shiomi, A., Hikichi, N.,
and Imai, M. PEAS-I: "A hardware/software codesign system for ASIP
development", IEICE Transactions on Fundamentals of Electronics,
Communications and Computer Science E77-A, 3 (March 1994),pp
483-491.
[15] Van prate.J, Goossens.G, Lanneer.D, and De man.H " Instruction set
definition and instruction set selection for ASIPs", In Proc. of the 7th
International Symposium on High-Level Synthesis 1994, pp. 11-16.
@article{"International Journal of Information, Control and Computer Sciences:62210", author = "Kamaraju.M and Lal Kishore.K and Tilak.A.V.N", title = "A Novel Implementation of Application Specific Instruction-set Processor (ASIP) using Verilog", abstract = "The general purpose processors that are used in
embedded systems must support constraints like execution time,
power consumption, code size and so on. On the other hand an
Application Specific Instruction-set Processor (ASIP) has advantages
in terms of power consumption, performance and flexibility. In this
paper, a 16-bit Application Specific Instruction-set processor for the
sensor data transfer is proposed. The designed processor architecture
consists of on-chip transmitter and receiver modules along with the
processing and controlling units to enable the data transmission and
reception on a single die. The data transfer is accomplished with less
number of instructions as compared with the general purpose
processor. The ASIP core operates at a maximum clock frequency of
1.132GHz with a delay of 0.883ns and consumes 569.63mW power
at an operating voltage of 1.2V. The ASIP is implemented in Verilog
HDL using the Xilinx platform on Virtex4.", keywords = "ASIP, Data transfer, Instruction set, Processor", volume = "5", number = "11", pages = "1412-6", }