Abstract: The ventilated façade has great advantages when
compared to traditional façades as it reduces the air conditioning
thermal loads due to the stack effect induced by solar radiation in the
air chamber. Optimizing energy consumption by using a ventilated
façade can be used not only in newly built buildings but also it can be
implemented in existing buildings, opening the field of
implementation to energy building retrofitting works. In this sense, the following three prototypes of façade where
designed, built and further analyzed in this research: non-ventilated
façade (NVF); slightly ventilated façade (SLVF) and strongly
ventilated façade (STVF). The construction characteristics of the
three facades are based on the Spanish regulation of building
construction “Technical Building Code”. The façades have been
monitored by type-k thermocouples in a representative day of the
summer season in Madrid (Spain). Moreover, an analysis of variance
(ANOVA) with repeated measures, studying the thermal lag in the
ventilated and no-ventilated façades has been designed. Results show that STVF façade presents higher levels of thermal
inertia as the thermal lag reduces up to 17% (daily mean) compared
to the non-ventilated façade. In addition, the statistical analysis
proves that an increase of the ventilation holes size in STVF façades
can improve the thermal lag significantly (p >0.05) when compared
to the SLVF façade.
Abstract: This study examines the stack ventilation performance of an office building located in Taipei, Taiwan. Atriums in this building act as stacks that facilitate buoyancy-driven ventilation. Computational Fluid Dynamic (CFD) simulations are used to identify interior airflow patterns, and then used these patterns to assess the building’s heat expulsion efficiency. Ambient temperatures of 20°C were adopted as the typical seasonal spring temperature range in Taipei. Further, “zero-wind” conditions are established to ensure simulation results reflected only the buoyancy effect. After checking results against neutral pressure level (NPL) level, airflow, air velocity, and indoor temperature stratification, the lower stack is modified to reduce the NPL in order to remove heat accumulated on the top floor.
Abstract: In CMOS integrated circuit design there is a trade-off between static power consumption and technology scaling. Recently, the power density has increased due to combination of higher clock speeds, greater functional integration, and smaller process geometries. As a result static power consumption is becoming more dominant. This is a challenge for the circuit designers. However, the designers do have a few methods which they can use to reduce this static power consumption. But all of these methods have some drawbacks. In order to achieve lower static power consumption, one has to sacrifice design area and circuit performance. In this paper, we propose a new method to reduce static power in the CMOS VLSI circuit using Variable Body Biasing technique without being penalized in area requirement and circuit performance.