A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs
Time interleaved sigma-delta (TIΣΔ) architecture is a
potential candidate for high bandwidth analog to digital converters
(ADC) which remains a bottleneck for software and cognitive radio
receivers. However, the performance of the TIΣΔ architecture is
limited by the unavoidable gain and offset mismatches resulting
from the manufacturing process. This paper presents a novel digital
calibration method to compensate the gain and offset mismatch
effect. The proposed method takes advantage of the reconstruction
digital signal processing on each channel and requires only few logic
components for implementation. The run time calibration is estimated
to 10 and 15 clock cycles for offset cancellation and gain mismatch
calibration respectively.
[1] J. Mitola, "The software radio architecture," Communications Magazine,
IEEE, vol. 33, pp. 26-38, 1995.
[2] J. Mitola III and Jr Maguire, "Cognitive radio: making software radios
more personal," IEEE personal communications, vol. 6, pp. 13-18, 1999.
[3] A. Eshraghi and T. Fiez, "A time-interleaved parallel ΔΣ A/D converter,"
IEEE Trans. Circuit and Sys.II, vol. 50, pp. 118-129, March 2003.
[4] A. Eshraghi, "High-Speed Parallel Delta-Sigma Analog-To-Digital Converters,"
Phd thesis, Washinton State University, May 1999.
[5] V.T. Nguyen, P. Loumeau, and J.F. Naviner, "An interleaved delta-sigma
analog to digital converter with digital correction," IEEE International
Conference on Acoustics, Speech, and Signal Processing, vol. 4, 2002.
[6] V.T. Nguyen, P. Loumeau, and J.F. Naviner, "Analysis of time-interleaved
delta-sigma analog to digital converter," IEEE Vehicular Technology
Conference, vol. 4, pp. 1594-1597, 2002.
[7] I. Galton and H.T. Jensen, "Delta-sigma modulator based A/D conversion
without oversampling," IEEE Trans. Circuit and Sys.II, vol. 42, no. 12,
pp. 773-784, December 1995.
[8] P. Benabes, A. Beydoun and J. Oksman, "Extended frequency-banddecomposition
sigma-delta A/D converter," Analog Integrated Circuits
and Signal Processing, Springer,Jan 2009.
[9] V.T. Nguyen, P. Loumeau, J.F. Naviner and P. Benabes, "Convertisseur
sigma delta," Patent, Number Fr 08-53213, may 2008.
[10] C. Vogel and G. Kubin, "Modeling of time-interleaved ADCs with
nonlinear hybrid filter banks," AEUE-International Journal of Electronics
and Communications,Elsevier, vol. 59, no. 5, pp. 288-296, 2005.
[11] C. Vogel, "The impact of combined channel mismatch effects in
time-interleaved ADCs," IEEE Transactions on Instrumentation and
Measurement, vol. 54, no. 1, pp. 415-427, 2005.
[12] C. Vogel and H. Koeppl, "Behavioral modeling of time-interleaved
ADCs using MATLAB," Proc. Austrochip, pp. 45-48, 2003.
[13] A. Petraglia and SK. Mitra, "Analysis of mismatch effects among A/D
converters in a time-interleaved waveform digitizer," Instrumentation and
Measurement, IEEE Transactions on, vol. 40, no. 5, pp. 831-835, 1991.
[14] A. Beydoun, V. T. Nguyen, L. Naviner and P. Loumeau, "65 nm digital
processing for TIHPΣΔ A/D converters in multistandard applications,"
IEEE, ISCAS, International Symposium on Circuits and Systems, Taipei,
Taiwan, May 24-27,2009.
[15] RD. Batten, A. Eshraghi and TS. Fiez, "Calibration of Parallel ΣΔ
ADCs," IEEE Trans. Circuits Syst. II, vol. 49, no. 6, pp. 390-399, 2002.
[16] J.E. Eklund and F. Gustafsson, "Digital offset compensation of timeinterleaved
ADC using randomchopper sampling," Circuits and Systems,
2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International
Symposium on, vol. 3, 2000.
[17] A. Shoval, D.A. Johns and W.M. Snelgrove, "Comparison of DC offset
effects in four LMS adaptive algorithms," IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing,vol. 42, pp. 176-
185, 1995.
[18] V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati, and F. Maloberti,
"Gain and offset mismatch calibration in time-interleaved multipath A/D
sigma-delta modulators," IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 51, no. 12, pp. 2365-2373, 2004.
[19] D. Fu, KC. Dyer, SH. Lewis and PJ. Hurst, "A digital background
calibration technique for time-interleavedanalog-to-digital converters,"
IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911,
1998.
[20] A. Beydoun, V.T. Nguyen and P. Loumeau, "A Novel Digital Calibration
Technique for Gain and Offset Mismatch in Parallel TIΣΔ ADCs,"
IEEE, ICASSP,, 2010.
[21] A. Eshraghi and T. Fiez, "A comparative analysis of parallel delta-sigma
ADC architectures," IEEE Trans. Circuit and Sys.I, vol. 51, pp. 450-458,
March 2004.
[22] A. Beydoun, V.T. Nguyen and P. Loumeau, "Correction des defauts
analogiques dans des convertisseurs analogiques/numeriques paralleles,
notamment pour des applications multistandars, radio logicielle et/ou
radio-cognitive," Patent, Number Fr 09-55351, July 2009.
[23] A. Beydoun, C. Jabbour, H. Fakhoury, V.T. Nguyen, L. Naviner, and
P. Loumeau, "A 65 nm CMOS Versatile ADC using Time Interleaving
and ΣΔ modulation for Multi-mode Receiver," IEEE, NEWCAS-TAISA,
Toulouse, France, 28 June-1 July, 2009.
[1] J. Mitola, "The software radio architecture," Communications Magazine,
IEEE, vol. 33, pp. 26-38, 1995.
[2] J. Mitola III and Jr Maguire, "Cognitive radio: making software radios
more personal," IEEE personal communications, vol. 6, pp. 13-18, 1999.
[3] A. Eshraghi and T. Fiez, "A time-interleaved parallel ΔΣ A/D converter,"
IEEE Trans. Circuit and Sys.II, vol. 50, pp. 118-129, March 2003.
[4] A. Eshraghi, "High-Speed Parallel Delta-Sigma Analog-To-Digital Converters,"
Phd thesis, Washinton State University, May 1999.
[5] V.T. Nguyen, P. Loumeau, and J.F. Naviner, "An interleaved delta-sigma
analog to digital converter with digital correction," IEEE International
Conference on Acoustics, Speech, and Signal Processing, vol. 4, 2002.
[6] V.T. Nguyen, P. Loumeau, and J.F. Naviner, "Analysis of time-interleaved
delta-sigma analog to digital converter," IEEE Vehicular Technology
Conference, vol. 4, pp. 1594-1597, 2002.
[7] I. Galton and H.T. Jensen, "Delta-sigma modulator based A/D conversion
without oversampling," IEEE Trans. Circuit and Sys.II, vol. 42, no. 12,
pp. 773-784, December 1995.
[8] P. Benabes, A. Beydoun and J. Oksman, "Extended frequency-banddecomposition
sigma-delta A/D converter," Analog Integrated Circuits
and Signal Processing, Springer,Jan 2009.
[9] V.T. Nguyen, P. Loumeau, J.F. Naviner and P. Benabes, "Convertisseur
sigma delta," Patent, Number Fr 08-53213, may 2008.
[10] C. Vogel and G. Kubin, "Modeling of time-interleaved ADCs with
nonlinear hybrid filter banks," AEUE-International Journal of Electronics
and Communications,Elsevier, vol. 59, no. 5, pp. 288-296, 2005.
[11] C. Vogel, "The impact of combined channel mismatch effects in
time-interleaved ADCs," IEEE Transactions on Instrumentation and
Measurement, vol. 54, no. 1, pp. 415-427, 2005.
[12] C. Vogel and H. Koeppl, "Behavioral modeling of time-interleaved
ADCs using MATLAB," Proc. Austrochip, pp. 45-48, 2003.
[13] A. Petraglia and SK. Mitra, "Analysis of mismatch effects among A/D
converters in a time-interleaved waveform digitizer," Instrumentation and
Measurement, IEEE Transactions on, vol. 40, no. 5, pp. 831-835, 1991.
[14] A. Beydoun, V. T. Nguyen, L. Naviner and P. Loumeau, "65 nm digital
processing for TIHPΣΔ A/D converters in multistandard applications,"
IEEE, ISCAS, International Symposium on Circuits and Systems, Taipei,
Taiwan, May 24-27,2009.
[15] RD. Batten, A. Eshraghi and TS. Fiez, "Calibration of Parallel ΣΔ
ADCs," IEEE Trans. Circuits Syst. II, vol. 49, no. 6, pp. 390-399, 2002.
[16] J.E. Eklund and F. Gustafsson, "Digital offset compensation of timeinterleaved
ADC using randomchopper sampling," Circuits and Systems,
2000. Proceedings. ISCAS 2000 Geneva. The 2000 IEEE International
Symposium on, vol. 3, 2000.
[17] A. Shoval, D.A. Johns and W.M. Snelgrove, "Comparison of DC offset
effects in four LMS adaptive algorithms," IEEE Transactions on Circuits
and Systems II: Analog and Digital Signal Processing,vol. 42, pp. 176-
185, 1995.
[18] V. Ferragina, A. Fornasari, U. Gatti, P. Malcovati, and F. Maloberti,
"Gain and offset mismatch calibration in time-interleaved multipath A/D
sigma-delta modulators," IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 51, no. 12, pp. 2365-2373, 2004.
[19] D. Fu, KC. Dyer, SH. Lewis and PJ. Hurst, "A digital background
calibration technique for time-interleavedanalog-to-digital converters,"
IEEE Journal of Solid-State Circuits, vol. 33, no. 12, pp. 1904-1911,
1998.
[20] A. Beydoun, V.T. Nguyen and P. Loumeau, "A Novel Digital Calibration
Technique for Gain and Offset Mismatch in Parallel TIΣΔ ADCs,"
IEEE, ICASSP,, 2010.
[21] A. Eshraghi and T. Fiez, "A comparative analysis of parallel delta-sigma
ADC architectures," IEEE Trans. Circuit and Sys.I, vol. 51, pp. 450-458,
March 2004.
[22] A. Beydoun, V.T. Nguyen and P. Loumeau, "Correction des defauts
analogiques dans des convertisseurs analogiques/numeriques paralleles,
notamment pour des applications multistandars, radio logicielle et/ou
radio-cognitive," Patent, Number Fr 09-55351, July 2009.
[23] A. Beydoun, C. Jabbour, H. Fakhoury, V.T. Nguyen, L. Naviner, and
P. Loumeau, "A 65 nm CMOS Versatile ADC using Time Interleaving
and ΣΔ modulation for Multi-mode Receiver," IEEE, NEWCAS-TAISA,
Toulouse, France, 28 June-1 July, 2009.
@article{"International Journal of Electrical, Electronic and Communication Sciences:61019", author = "Ali Beydoun and Van-Tam Nguyen and Patrick Loumeau", title = "A Novel Digital Calibration Technique for Gain and Offset Mismatch in TIΣΔ ADCs", abstract = "Time interleaved sigma-delta (TIΣΔ) architecture is a
potential candidate for high bandwidth analog to digital converters
(ADC) which remains a bottleneck for software and cognitive radio
receivers. However, the performance of the TIΣΔ architecture is
limited by the unavoidable gain and offset mismatches resulting
from the manufacturing process. This paper presents a novel digital
calibration method to compensate the gain and offset mismatch
effect. The proposed method takes advantage of the reconstruction
digital signal processing on each channel and requires only few logic
components for implementation. The run time calibration is estimated
to 10 and 15 clock cycles for offset cancellation and gain mismatch
calibration respectively.", keywords = "sigma-delta, calibration, gain and offset mismatches,analog-to-digital conversion, time-interleaving.", volume = "5", number = "9", pages = "1238-11", }
