SCR-Stacking Structure with High Holding Voltage for I/O and Power Clamp

In this paper, we proposed a novel SCR (Silicon Controlled Rectifier) - based ESD (Electrostatic Discharge) protection device for I/O and power clamp. The proposed device has a higher holding voltage characteristic than conventional SCR. These characteristics enable to have latch-up immunity under normal operating conditions as well as superior full chip ESD protection. The proposed device was analyzed to figure out electrical characteristics and tolerance robustness in term of individual design parameters (D1, D2, D3). They are investigated by using the Synopsys TCAD simulator. As a result of simulation, holding voltage increased with different design parameters. The holding voltage of the proposed device changes from 3.3V to 7.9V. Also, N-Stack structure ESD device with the high holding voltage is proposed. In the simulation results, 2-stack has holding voltage of 6.8V and 3-stack has holding voltage of 10.5V. The simulation results show that holding voltage of stacking structure can be larger than the operation voltage of high-voltage application.

Comparative Review of Modulation Techniques for Harmonic Minimization in Multilevel Inverter

This paper proposed the comparison made between Multi-Carrier Pulse Width Modulation, Sinusoidal Pulse Width Modulation and Selective Harmonic Elimination Pulse Width Modulation technique for minimization of Total Harmonic Distortion in Cascaded H-Bridge Multi-Level Inverter. In Multicarrier Pulse Width Modulation method by using Alternate Position of Disposition scheme for switching pulse generation to Multi-Level Inverter. Another carrier based approach; Sinusoidal Pulse Width Modulation method is also implemented to define the switching pulse generation system in the multi-level inverter. In Selective Harmonic Elimination method using Genetic Algorithm and Particle Swarm Optimization algorithm for define the required switching angles to eliminate low order harmonics from the inverter output voltage waveform and reduce the total harmonic distortion value. So, the results validate that the Selective Harmonic Elimination Pulse Width Modulation method does capably eliminate a great number of precise harmonics and minimize the Total Harmonic Distortion value in output voltage waveform in compared with Multi-Carrier Pulse Width Modulation method, Sinusoidal Pulse Width Modulation method. In this paper, comparison of simulation results shows that the Selective Harmonic Elimination method can attain optimal harmonic minimization solution better than Multi-Carrier Pulse Width Modulation method, Sinusoidal Pulse Width Modulation method.

Electric Field Impact on the Biomass Gasification and Combustion Dynamics

Experimental investigations of the DC electric field effect on thermal decomposition of biomass, formation of the axial flow of volatiles (CO, H2, CxHy), mixing of volatiles with swirling airflow at low swirl intensity (S ≈ 0.2-0.35), their ignition and on formation of combustion dynamics are carried out with the aim to understand the mechanism of electric field influence on biomass gasification, combustion of volatiles and heat energy production. The DC electric field effect on combustion dynamics was studied by varying the positive bias voltage of the central electrode from 0.6 kV to 3 kV, whereas the ion current was limited to 2 mA. The results of experimental investigations confirm the field-enhanced biomass gasification with enhanced release of volatiles and the development of endothermic processes at the primary stage of thermochemical conversion of biomass determining the field-enhanced heat energy consumption with the correlating decrease of the flame temperature and heat energy production at this stage of flame formation. Further, the field-enhanced radial expansion of the flame reaction zone correlates with a more complete combustion of volatiles increasing the combustion efficiency by 3% and decreasing the mass fraction of CO, H2 and CxHy in the products, whereas by 10% increases the average volume fraction of CO2 and the heat energy production downstream the combustor increases by 5-10% 

Optimal Planning of Dispatchable Distributed Generators for Power Loss Reduction in Unbalanced Distribution Networks

This paper proposes a novel heuristic algorithm that aims to determine the best size and location of distributed generators in unbalanced distribution networks. The proposed heuristic algorithm can deal with the planning cases where power loss is to be optimized without violating the system practical constraints. The distributed generation units in the proposed algorithm is modeled as voltage controlled node with the flexibility to be converted to constant power factor node in case of reactive power limit violation. The proposed algorithm is implemented in MATLAB and tested on the IEEE 37 -node feeder. The results obtained show the effectiveness of the proposed algorithm. 

Wind Diesel Hybrid System without Battery Energy Storage Using Imperialist Competitive Algorithm

Nowadays, the use of renewable energy sources has been increasingly great because of the cost increase and public demand for clean energy sources. One of the fastest growing sources is wind energy. In this paper, Wind Diesel Hybrid System (WDHS) comprising a Diesel Generator (DG), a Wind Turbine Generator (WTG), the Consumer Load, a Battery-based Energy Storage System (BESS), and a Dump Load (DL) is used. Voltage is controlled by Diesel Generator; the frequency is controlled by BESS and DL. The BESS elimination is an efficient way to reduce maintenance cost and increase the dynamic response. Simulation results with graphs for the frequency of Power System, active power, and the battery power are presented for load changes. The controlling parameters are optimized by using Imperialist Competitive Algorithm (ICA). The simulation results for the BESS/no BESS cases are compared. Results show that in no BESS case, the frequency control is more optimal than the BESS case by using ICA. 

Experimental Implementation of Model Predictive Control for Permanent Magnet Synchronous Motor

Fast speed drives for Permanent Magnet Synchronous Motor (PMSM) is a crucial performance for the electric traction systems. In this paper, PMSM is derived with a Model-based Predictive Control (MPC) technique. Fast speed tracking is achieved through optimization of the DC source utilization using MPC. The technique is based on predicting the optimum voltage vector applied to the driver. Control technique is investigated by comparing to the cascaded PI control based on Space Vector Pulse Width Modulation (SVPWM). MPC and SVPWM-based FOC are implemented with the TMS320F2812 DSP and its power driver circuits. The designed MPC for a PMSM drive is experimentally validated on a laboratory test bench. The performances are compared with those obtained by a conventional PI-based system in order to highlight the improvements, especially regarding speed tracking response.

Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to the symmetrical input stage. P-Spice simulation results are obtained using 0.18μm MIETEC CMOS process parameters and supply voltage of ±1.2V, 50μA biasing current. The p-spice simulation shows excellent improvement of the proposed CFOA over existing CMOS CFOA. Some of these performance parameters, for example, are DC gain of 62. dB, openloop gain bandwidth product of 108 MHz, slew rate (SR+) of +71.2V/μS, THD of -63dB and DC consumption power (PC) of 2mW.

Simulink Model of Reference Frame Theory Based Three Phase Shunt Active Filter

Among various active filters, shunt active filter is a viable solution for reactive power and harmonics compensation. In this paper, the SRF plan is used to generate current reference for compensation and conventional PI controllers were used as the controller to compensate the reactive power. The design of the closed loop controllers is reserved simple by modeling them as first order systems. Computationally uncomplicated and efficient SVM system is used in the present work for better utilization of dc bus voltage. The rating of shunt active filter has been finalized based on the reactive power demand of the selected reactive load. The proposed control and SVM technique are validated by simulating in MATLAB software.

Comparative Study between Classical P-Q Method and Modern Fuzzy Controller Method to Improve the Power Quality of an Electrical Network

This article presents two methods for the compensation of harmonics generated by a nonlinear load. The first is the classic method P-Q. The second is the controller by modern method of artificial intelligence specifically fuzzy logic. Both methods are applied to a shunt Active Power Filter (sAPF) based on a three-phase voltage converter at five levels NPC topology. In calculating the harmonic currents of reference, we use the algorithm P-Q and pulse generation, we use the intersective PWM. For flexibility and dynamics, we use fuzzy logic. The results give us clear that the rate of Harmonic Distortion issued by fuzzy logic is better than P-Q.

Highly Optimized Novel High Speed Low Power Barrel Shifter at 22nm Hi K Metal Gate Strained Si Technology Node

This research paper presents highly optimized barrel shifter at 22nm Hi K metal gate strained Si technology node. This barrel shifter is having a unique combination of static and dynamic body bias which gives lowest power delay product. This power delay product is compared with the same circuit at same technology node with static forward biasing at ‘supply/2’ and also with normal reverse substrate biasing and still found to be the lowest. The power delay product of this barrel sifter is .39362X10-17J and is lowered by approximately 78% to reference proposed barrel shifter at 32nm bulk CMOS technology. Power delay product of barrel shifter at 22nm Hi K Metal gate technology with normal reverse substrate bias is 2.97186933X10-17J and can be compared with this design’s PDP of .39362X10-17J. This design uses both static and dynamic substrate biasing and also has approximately 96% lower power delay product compared to only forward body biased at half of supply voltage. The NMOS model used are predictive technology models of Arizona state university and the simulations to be carried out using HSPICE simulator.

Multiple-Channel Piezoelectric Actuated Tunable Optical Filter for WDM Application

We propose new multiple-channel piezoelectric (PZT) actuated tunable optical filter based on racetrack multi-ring resonators for wavelength de-multiplexing network applications. We design tunable eight-channel wavelength de-multiplexer consisting of eight cascaded PZT actuated tunable multi-ring resonator filter with a channel spacing of 1.6nm. The filter for each channel is basically structured on a suspended beam, sandwiched with piezoelectric material and built in integrated ring resonators which are placed on the middle of the beam to gain uniform stress and linearly varying longitudinal strain. A reference single mode serially coupled multi stage racetrack ring resonator with the same radii and coupling length is designed with a line width of 0.8974nm with a flat top pass band at 1dB of 0.5205nm and free spectral range of about 14.9nm. In each channel, a small change in the perimeter of the rings is introduced to establish the shift in resonance wavelength as per the defined channel spacing. As a result, when a DC voltage is applied, the beams will elongate, which involves mechanical deformation of the ring resonators that induces a stress and a strain, which brings a change in refractive index and perimeter of the rings leading to change in the output spectrum shift providing the tunability of central wavelength in each channel. Simultaneous wave length shift as high as 45.54pm/

Improvement of Voltage Profile of Grid Integrated Wind Distributed Generation by SVC

Due to the continuous increment of the load demand, identification of weaker buses, improvement of voltage profile and power losses in the context of the voltage stability problems has become one of the major concerns for the larger, complex, interconnected power systems. The objective of this paper is to review the impact of Flexible AC Transmission System (FACTS) controller in Wind generators connected electrical network for maintaining voltage stability. Wind energy could be the growing renewable energy due to several advantages. The influence of wind generators on power quality is a significant issue; non uniform power production causes variations in system voltage and frequency. Therefore, wind farm requires high reactive power compensation; the advances in high power semiconducting devices have led to the development of FACTS. The FACTS devices such as for example SVC inject reactive power into the system which helps in maintaining a better voltage profile. The performance is evaluated on an IEEE 14 bus system, two wind generators are connected at low voltage buses to meet the increased load demand and SVC devices are integrated at the buses with wind generators to keep voltage stability. Power flows, nodal voltage magnitudes and angles of the power network are obtained by iterative solutions using MIPOWER.

Compensation of Power Quality Disturbances Using DVR

One of the key aspects of power quality improvement in power system is the mitigation of voltage sags/swells and flicker. Custom power devices have been known as the best tools for voltage disturbances mitigation as well as reactive power compensation. Dynamic Voltage Restorer (DVR) which is the most efficient and effective modern custom power device can provide the most commercial solution to solve several problems of power quality in distribution networks. This paper deals with analysis and simulation technique of DVR based on instantaneous power theory which is a quick control to detect signals. The main purpose of this work is to remove three important disturbances including voltage sags/swells and flicker. Simulation of the proposed method was carried out on two sample systems by using Matlab software environment and the results of simulation show that the proposed method is able to provide desirable power quality in the presence of wide range of disturbances.

Nonlinear Modeling of the PEMFC Based On NNARX Approach

Polymer Electrolyte Membrane Fuel Cell (PEMFC) is such a time-vary nonlinear dynamic system. The traditional linear modeling approach is hard to estimate structure correctly of PEMFC system. From this reason, this paper presents a nonlinear modeling of the PEMFC using Neural Network Auto-regressive model with eXogenous inputs (NNARX) approach. The multilayer perception (MLP) network is applied to evaluate the structure of the NNARX model of PEMFC. The validity and accuracy of NNARX model are tested by one step ahead relating output voltage to input current from measured experimental of PEMFC. The results show that the obtained nonlinear NNARX model can efficiently approximate the dynamic mode of the PEMFC and model output and system measured output consistently.

Time-Domain Analysis of Pulse Parameters Effects on Crosstalk (In High Speed Circuits)

Crosstalk among interconnects and printed-circuit board (PCB) traces is a major limiting factor of signal quality in highspeed digital and communication equipments especially when fast data buses are involved. Such a bus is considered as a planar multiconductor transmission line. This paper will demonstrate how the finite difference time domain (FDTD) method provides an exact solution of the transmission-line equations to analyze the near end and the far end crosstalk. In addition, this study makes it possible to analyze the rise time effect on the near and far end voltages of the victim conductor. The paper also discusses a statistical analysis, based upon a set of several simulations. Such analysis leads to a better understanding of the phenomenon and yields useful information.

Induction Motor Analysis Using LabVIEW

Proposed paper dealt with the modelling and analysis of induction motor based on the mathematical expression using the graphical programming environment of Laboratory Virtual Instrument Engineering Workbench (LabVIEW). Induction motor modelling with the mathematical expression enables the motor to be simulated with the various required parameters. Owing to the invention of variable speed drives study about the induction motor characteristics became complex. In this simulation motor internal parameter such as stator resistance and reactance, rotor resistance and reactance, phase voltage, frequency and losses will be given as input. By varying the speed of motor corresponding parameters can be obtained they are input power, output power, efficiency, torque induced, slip and current.

A High Level Implementation of a High Performance Data Transfer Interface for NoC

The distribution of a single global clock across a chip has become the major design bottleneck for high performance VLSI systems owing to the power dissipation, process variability and multicycle cross-chip signaling. A Network-on-Chip (NoC) architecture partitioned into several synchronous blocks has become a promising approach for attaining fine-grain power management at the system level. In a NoC architecture the communication between the blocks is handled asynchronously. To interface these blocks on a chip operating at different frequencies, an asynchronous FIFO interface is inevitable. However, these asynchronous FIFOs are not required if adjacent blocks belong to the same clock domain. In this paper, we have designed and analyzed a 16-bit asynchronous micropipelined FIFO of depth four, with the awareness of place and route on an FPGA device. We have used a commercially available Spartan 3 device and designed a high speed implementation of the asynchronous 4-phase micropipeline. The asynchronous FIFO implemented on the FPGA device shows 76 Mb/s throughput and a handshake cycle of 109 ns for write and 101.3 ns for read at the simulation under the worst case operating conditions (voltage = 0.95V) on a working chip at the room temperature.

Dynamic Performance Evaluation of Distributed Generation Units in the Micro Grid

This paper presents dynamic models of distributed generators (DG) and investigates dynamic behavior of the DG units in the micro grid system. The DG units include photovoltaic and fuel cell sources. The voltage source inverter is adopted since the electronic interface which can be equipped with its controller to keep stability of the micro grid during small signal dynamics. This paper also introduces power management strategies and implements the DG load sharing concept to keep the micro grid operation in gridconnected and islanding modes of operation. The results demonstrate the operation and performance of the photovoltaic and fuel cell as distributed generators in a micro grid. The entire control system in the micro grid is developed by combining the benefits of the power control and the voltage control strategies. Simulation results are all reported, confirming the validity of the proposed control technique.

A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling

Today’s VLSI networks demands for high speed. And in this work the compact form mathematical model for current mode signalling in VLSI interconnects is presented.RLC interconnect line is modelled using characteristic impedance of transmission line and inductive effect. The on-chip inductance effect is dominant at lower technology node is emulated into an equivalent resistance. First order transfer function is designed using finite difference equation, Laplace transform and by applying the boundary conditions at the source and load termination. It has been observed that the dominant pole determines system response and delay in the proposed model. The novel proposed current mode model shows superior performance as compared to voltage mode signalling. Analysis shows that current mode signalling in VLSI interconnects provides 2.8 times better delay performance than voltage mode. Secondly the damping factor of a lumped RLC circuit is shown to be a useful figure of merit.

Advanced Pulse Width Modulation Techniques for Z Source Multi Level Inverter

This paper proposes five level diode clamped Z source Inverter. The existing PWM techniques used for ZSI are restricted for two level. The two level Z Source Inverter have high harmonic distortions which effects the performance of the grid connected PV system. To improve the performance of the system the number of voltage levels in the output waveform need to be increased. This paper presents comparative analysis of a five level diode clamped Z source Inverter with different carrier based Modified Pulse Width Modulation techniques. The parameters considered for comparison are output voltage, voltage gain, voltage stress across switch and total harmonic distortion when powered by same DC supply. Analytical results are verified using MATLAB.