A Superior Delay Estimation Model for VLSI Interconnect in Current Mode Signaling

Today’s VLSI networks demands for high speed. And
in this work the compact form mathematical model for current mode
signalling in VLSI interconnects is presented.RLC interconnect line
is modelled using characteristic impedance of transmission line and
inductive effect. The on-chip inductance effect is dominant at lower
technology node is emulated into an equivalent resistance. First order
transfer function is designed using finite difference equation, Laplace
transform and by applying the boundary conditions at the source and
load termination. It has been observed that the dominant pole
determines system response and delay in the proposed model. The
novel proposed current mode model shows superior performance as
compared to voltage mode signalling. Analysis shows that current
mode signalling in VLSI interconnects provides 2.8 times better
delay performance than voltage mode. Secondly the damping factor
of a lumped RLC circuit is shown to be a useful figure of merit.

• Sunil Jadav
• Rajeevan Chandel Munish Vashishath

• Current Mode
• Voltage Mode
• VLSI Interconnect.

[1] D.Liu and C. Svensson Power Consumption Estimation in CMOS VLSI
Chips. IEEE Journal of Solid State Circuits1994,29(6),pp. 663–670.
[2] D. Sylvester and K. Kuetzer “Getting to the Bottom of Deep Submicron
II: The Global Wiring Paradigm”. in Proc. International Symposium on
Physical Design, April 1999, pp. 193–200.
[3] R. Bashirullah, W. Liu, and R. K. Cavin Current Mode Signaling in
Deep Submicrometer Global Interconnects. IEEE Transactions on VLSI
Systems,2003, 11(3) pp. 406–417.
[4] I. Dhaou, M. Ismail, and H. Tenhunen. Current Mode, Low Power, On-
Chip Signaling in Deep Sub-micron CMOS Technology. IEEE
Transactions on Circuits and Systems, 2001, 50(3) pp. 397–406.
[5] V. Venkatraman and W. Burleson, Robust Multi-Level Current-Mode
On-Chip Interconnect Signaling in the Presence of Process Variations,
inProc. of Sixth International Symposium on Quality Electronic Design,
March 2005, pp. 522–527.
[6] E. Seevinck, P. van Beers, and H. Ontrop. Current Mode Techniques for
High Speed VLSI Circuits with Application to Current Sense Amplifier
for CMOS SRAMs. in IEEE Journal Of Solid State Circuits, 1991,
26(4)pp. 525–536.
[7] H.Schmid, Why the terms ‘Current mode’ and ‘voltage Mode’ Neither
Divide nor qualify circuits, in Proc. of IEEE, 2002, pp. 29-32.
[8] M.M Tabrizi, N. Masoumi, M. Deilami, High Speed Current Mode
Signalling for Interconnects Considering transmission line and Crosstalk
effects, in Proc. of IEEE 2007, pp. 17-20.
[9] M.M Tabrizi, N. Masoumi, Low-power and high-performance
techniques in global interconnect signalling in Microelectronics Journal,
(2009) pp.1-9.
[10] Tomoaki Maekawa et al., Highly Energy-Efficient On-Chip Pulsed-
Current-Mode Transmission Line Interconnect, solid state circuit
technologies (book), pp 263-280, January 2010.
[11] Marshnil Dave et al., Energy efficient current mode signaling scheme,
IEEE Asian Solid State circuit conference, November 8-10, 2010.
[12] Naveen K.Kancharapu et.al, A Low-Power Low Skew Current-Mode
Clock Distribution Network in 90nm CMOS Technology, in IEEE Proc.
ISVLSI 2011, pp 132-137.
[13] R.Venkatesan, J. Davis, and J.Mendil, Compact distributed RLC
interconnect models part IV: unified models for time delay, crosstalk,
and repeater insertion, IEEE Trans. Electron Devices, 50 (2003) pp.
1094-1102.
[14] R. Bashirullah, W. Liu, and R. K., Delay and power model for current
mode signaling in deep submicron global interconnects, Proceedings of
IEEE Custom Integrated Circuits Conference, May 2002, pp. 513-516.
[15] M.Zhou,W.Liu and M.Sivaprakasam,A Closed-form Delay Formula for
On-Chip RLC Interconnectsin Current-Mode Signaling in IEEE Proc.
2005, pp 1082-1085.
[16] S.Jadav,M.Vashishth, Rajeevan Chandel, Close form delay model for on
chip signalling with resistive load termination using: Current mode
technique” in IEEE Proc. of ICIIS 2014, pp-1-6.
[17] M. Ismail, N. Tan, Modeling Techniques for energy efficient system-ona-
chip signaling, IEEE Circuits and Device Magazine, 19 (2003) pp. 8-
17.
[18] MATLAB version R2009a Online, http://mathwork.com, 2013.
[19] PTM models online: http://www.berkely edu.com, 2013.
[20] Tanner EDA tools online: http:// tannereda.com, 2013.
[21] Y. Ismail, E. Friedman, and J. Neves, “Figures of Merit to Characterize
the Importanceof On-Chip Inductance,” IEEE Trans. On VLSI system,
vol. 7(4), 1999, pp. 442-449.