Abstract: This paper reports on the impact study with the variation of the gate insulation material and thickness on different models of pocket implanted sub-100 nm n-MOS device. The gate materials used here are silicon dioxide (SiO2), aluminum silicate (Al2SiO5), silicon nitride (Si3N4), alumina (Al2O3), hafnium silicate (HfSiO4), tantalum pentoxide (Ta2O5), hafnium dioxide (HfO2), zirconium dioxide (ZrO2), and lanthanum oxide (La2O3) upon a p-type silicon substrate material. The gate insulation thickness was varied from 2.0 nm to 3.5 nm for a 50 nm channel length pocket implanted n-MOSFET. There are several models available for this device. We have studied and simulated threshold voltage model incorporating drain and substrate bias effects, surface potential, inversion layer charge, pinch-off voltage, effective electric field, inversion layer mobility, and subthreshold drain current models based on two linear symmetric pocket doping profiles. We have changed the values of the two parameters, viz. gate insulation material and thickness gradually fixing the other parameter at their typical values. Then we compared and analyzed the simulation results. This study would be helpful for the nano-scaled MOS device designers for various applications to predict the device behavior.
Abstract: This paper presents a speed estimation scheme based
on second-order sliding-mode Super Twisting Algorithm (STA) and
Model Reference Adaptive System (MRAS) estimation theory for
Sensorless control of multiphase induction machine. A stator current
observer is designed based on the STA, which is utilized to take the
place of the reference voltage model of the standard MRAS
algorithm. The observer is insensitive to the variation of rotor
resistance and magnetizing inductance when the states arrive at the
sliding mode. Derivatives of rotor flux are obtained and designed as
the state of MRAS, thus eliminating the integration. Compared with
the first-order sliding-mode speed estimator, the proposed scheme
makes full use of the auxiliary sliding-mode surface, thus alleviating
the chattering behavior without increasing the complexity. Simulation
results show the robustness and effectiveness of the proposed
scheme.
Abstract: Today’s VLSI networks demands for high speed. And
in this work the compact form mathematical model for current mode
signalling in VLSI interconnects is presented.RLC interconnect line
is modelled using characteristic impedance of transmission line and
inductive effect. The on-chip inductance effect is dominant at lower
technology node is emulated into an equivalent resistance. First order
transfer function is designed using finite difference equation, Laplace
transform and by applying the boundary conditions at the source and
load termination. It has been observed that the dominant pole
determines system response and delay in the proposed model. The
novel proposed current mode model shows superior performance as
compared to voltage mode signalling. Analysis shows that current
mode signalling in VLSI interconnects provides 2.8 times better
delay performance than voltage mode. Secondly the damping factor
of a lumped RLC circuit is shown to be a useful figure of merit.
Abstract: Rotor Flux based Model Reference Adaptive System
(RF-MRAS) is the most popularly used conventional speed
estimation scheme for sensor-less IM drives. In this scheme, the
voltage model equations are used for the reference model. This
encounters major drawbacks at low frequencies/speed which leads to
the poor performance of RF-MRAS. Replacing the reference model
using Neural Network (NN) based flux estimator provides an
alternate solution and addresses such drawbacks. This paper
identifies an NN based flux estimator using Single Neuron Cascaded
(SNC) Architecture. The proposed SNC-NN model replaces the
conventional voltage model in RF-MRAS to form a novel MRAS
scheme named as SNC-NN-MRAS. Through simulation the proposed
SNC-NN-MRAS is shown to be promising in terms of all major
issues and robustness to parameter variation. The suitability of the
proposed SNC-NN-MRAS based speed estimator and its advantages
over RF-MRAS for sensor-less induction motor drives is
comprehensively presented through extensive simulations.
Abstract: This paper presents a threshold voltage model of pocket implanted sub-100 nm n-MOSFETs incorporating the drain and substrate bias effects using two linear pocket profiles. Two linear equations are used to simulate the pocket profiles along the channel at the surface from the source and drain edges towards the center of the n-MOSFET. Then the effective doping concentration is derived and is used in the threshold voltage equation that is obtained by solving the Poisson-s equation in the depletion region at the surface. Simulated threshold voltages for various gate lengths fit well with the experimental data already published in the literature. The simulated result is compared with the two other pocket profiles used to derive the threshold voltage models of n-MOSFETs. The comparison shows that the linear model has a simple compact form that can be utilized to study and characterize the pocket implanted advanced ULSI devices.
Abstract: This paper presents two prototypes of low power low voltage current mode 9 bit pipelined a/d converters. The first and the second converters are configured of 1.5 bit and 2.5 bit stages, respectively. The a/d converter structures are composed of current mode building blocks and final comparator block which converts the analog current signal into digital voltage signal. All building blocks have been designed in CMOS AMS 0.35μm technology, then simulated to verify proposed concept. The performances of both converters are compared to performances of known current mode and voltage mode switched capacitance converter structures. Low power consumption and small chip area are advantages of the proposed converters.
Abstract: A simple analytical model has been developed to
optimize biasing conditions for obtaining maximum linearity among
lattice-matched, pseudomorphic and metamorphic HEMT types as
well as enhancement and depletion HEMT modes. A nonlinear
current-voltage model has been simulated based on extracted data to
study and select the most appropriate type and mode of HEMT in
terms of a given gate-source biasing voltage within the device so as
to employ the circuit for the highest possible output current or
voltage linear swing. Simulation results can be used as a basis for the
selection of optimum gate-source biasing voltage for a given type
and mode of HEMT with regard to a circuit design. The
consequences can also be a criterion for choosing the optimum type
or mode of HEMT for a predetermined biasing condition.
Abstract: A new voltage-mode triple-input single-output multifunction filter using only two current conveyors is presented. The proposed filter which possesses three inputs and single-output can generate all biquadratic filtering functions at the output terminal by selecting different input signal combinations. The validity of the proposed filter is verified through PSPICE simulations.