Abstract: This paper proposed the comparison made between
Multi-Carrier Pulse Width Modulation, Sinusoidal Pulse Width
Modulation and Selective Harmonic Elimination Pulse Width
Modulation technique for minimization of Total Harmonic Distortion
in Cascaded H-Bridge Multi-Level Inverter. In Multicarrier Pulse
Width Modulation method by using Alternate Position of Disposition
scheme for switching pulse generation to Multi-Level Inverter.
Another carrier based approach; Sinusoidal Pulse Width Modulation
method is also implemented to define the switching pulse generation
system in the multi-level inverter. In Selective Harmonic Elimination
method using Genetic Algorithm and Particle Swarm Optimization
algorithm for define the required switching angles to eliminate low
order harmonics from the inverter output voltage waveform and
reduce the total harmonic distortion value. So, the results validate that
the Selective Harmonic Elimination Pulse Width Modulation method
does capably eliminate a great number of precise harmonics and
minimize the Total Harmonic Distortion value in output voltage
waveform in compared with Multi-Carrier Pulse Width Modulation
method, Sinusoidal Pulse Width Modulation method. In this paper,
comparison of simulation results shows that the Selective Harmonic
Elimination method can attain optimal harmonic minimization
solution better than Multi-Carrier Pulse Width Modulation method,
Sinusoidal Pulse Width Modulation method.
Abstract: Multi-Level Inverter technology has been developed in the area of high-power medium-voltage energy scheme, because of their advantages such as devices of lower rating can be used thereby enabling the schemes to be used for high voltage applications. Reduced Total Harmonic Distortion (THD).Since the dv/dt is low; the Electromagnetic Interference from the scheme is low. To avoid the switching losses Lower switching frequencies can be used. In this paper present a survey of various topologies, control strategy and modulation techniques used by these inverters. Here the regenerative and superior topologies are also discussed.
Abstract: In this paper family of multilevel inverter topology
with reduced number of power switches is presented. The proposed
inverter can generate both even and odd level. The proposed topology
is suitable for symmetric structure. The proposed symmetric inverter
results in reduction of power switches, power diode and gate driver
circuits and also it may further minimize the installation area and
cost. To prove the superiority of proposed topology is compared with
conventional topologies. The performance of this symmetric
multilevel inverter has been tested by computer based simulation and
prototype based experimental setup for nine-level inverter is
developed and results are verified.