Abstract: This research paper presents highly optimized barrel
shifter at 22nm Hi K metal gate strained Si technology node. This
barrel shifter is having a unique combination of static and dynamic
body bias which gives lowest power delay product. This power delay
product is compared with the same circuit at same technology node
with static forward biasing at ‘supply/2’ and also with normal reverse
substrate biasing and still found to be the lowest. The power delay
product of this barrel sifter is .39362X10-17J and is lowered by
approximately 78% to reference proposed barrel shifter at 32nm bulk
CMOS technology. Power delay product of barrel shifter at 22nm Hi
K Metal gate technology with normal reverse substrate bias is
2.97186933X10-17J and can be compared with this design’s PDP of
.39362X10-17J. This design uses both static and dynamic substrate
biasing and also has approximately 96% lower power delay product
compared to only forward body biased at half of supply voltage. The
NMOS model used are predictive technology models of Arizona state
university and the simulations to be carried out using HSPICE
simulator.