Abstract: In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
Abstract: The threshold voltage and capacitance voltage characteristics of ultra-thin Silicon-on-Insulator MOSFET are greatly influenced by the thickness and doping concentration of the silicon film. In this work, the capacitance voltage characteristics and threshold voltage of the device have been analyzed with quantum mechanical effects using the Self-Consistent model. Reduction of channel thickness and adding doping impurities cause an increase in the threshold voltage. Moreover, the temperature effects cause a significant amount of threshold voltage shift. The temperature dependence of threshold voltage has also been observed with Self- Consistent approach which are well supported from experimental performance of practical devices.
Abstract: A lateral trench-gate power metal-oxide-semiconductor on 4H-SiC is proposed. The device consists of two separate trenches in which two gates are placed on both sides of P-body region resulting two parallel channels. Enhanced current conduction and reduced-surface-field effect in the structure provide substantial improvement in the device performance. Using two dimensional simulations, the performance of proposed device is evaluated and compare of with that of the conventional device for same cell pitch. It is demonstrated that the proposed structure provides two times higher output current, 11% decrease in threshold voltage, 70% improvement in transconductance, 70% reduction in specific ON-resistance, 52% increase in breakdown voltage, and nearly eight time improvement in figure-of-merit over the conventional device.
Abstract: Ultra-low-power (ULP) circuits have received
widespread attention due to the rapid growth of biomedical
applications and Battery-less Electronics. Subthreshold region of
transistor operation is used in ULP circuits. Major research challenge
in the subthreshold operating region is to extract the ULP benefits
with minimal degradation in speed and robustness. Process, Voltage
and Temperature (PVT) variations significantly affect the
performance of subthreshold circuits. Designed performance
parameters of ULP circuits may vary largely due to temperature
variations. Hence, this paper investigates the effect of temperature
variation on device and circuit performance parameters at different
biasing voltages in the subthreshold region. Simulation results clearly
demonstrate that in deep subthreshold and near threshold voltage
regions, performance parameters are significantly affected whereas in
moderate subthreshold region, subthreshold circuits are more
immune to temperature variations. This establishes that moderate
subthreshold region is ideal for temperature immune circuits.
Abstract: This paper describes a novel monitoring scheme to
minimize total active power in digital circuits depend on the demand
frequency, by adjusting automatically both supply voltage and
threshold voltages based on circuit operating conditions such as
temperature, process variations, and desirable frequency. The delay
monitoring results, will be control and apply so as to be maintained at
the minimum value at which the chip is able to operate for a given
clock frequency. Design details of power monitor are examined using
simulation framework in 32nm BTPM model CMOS process.
Experimental results show the overhead of proposed circuit in terms
of its power consumption is about 40 μW for 32nm technology;
moreover the results show that our proposed circuit design is not far
sensitive to the temperature variations and also process variations.
Besides, uses the simple blocks which offer good sensitivity, high
speed, the continuously feedback loop. This design provides up to
40% reduction in power consumption in active mode.
Abstract: In this paper, a new BiCMOS CCII and CCCII,
capable of operate at ±0.5V and having wide dynamic range with
achieved bandwidth of 480MHz and 430MHz respectively have been
proposed. The structures have been found to be insensitive to the
threshold voltage variations. The proposed circuits are suitable for
implementation using 0.25μm BiCMOS technology. Pspice
simulations confirm the performance of the proposed structures.
Abstract: In this paper, we have developed an explicit analytical
drain current model comprising surface channel potential and
threshold voltage in order to explain the advantages of the proposed
Gate Stack Double Diffusion (GSDD) MOSFET design over the
conventional MOSFET with the same geometric specifications that
allow us to use the benefits of the incorporation of the high-k layer
between the oxide layer and gate metal aspect on the immunity of the
proposed design against the self-heating effects. In order to show the
efficiency of our proposed structure, we propose the simulation of the
power chopper circuit. The use of the proposed structure to design a
power chopper circuit has showed that the (GSDD) MOSFET can
improve the working of the circuit in terms of power dissipation and
self-heating effect immunity. The results so obtained are in close
proximity with the 2D simulated results thus confirming the validity
of the proposed model.
Abstract: The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable ION/IOFF ratio of (104) and low drain induced barrier lowering (DIBL) of 39 mV/V.