Abstract: Invention of transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key for the development of nanoelectronics technology. In the first part of this manuscript, we present a new generation of MOSFET transistors based on SOI (Silicon-On-Insulator) technology. It is a partially depleted Silicon-On-Insulator (PD SOI MOSFET) transistor simulated by using SILVACO software. This work was completed by the presentation of some results concerning the influence of parameters variation (channel length L and gate oxide thickness Tox) on our PDSOI n-MOSFET structure on its drain current and kink effect.
Abstract: The progress of industry integrated circuits in recent
years has been pushed by continuous miniaturization of transistors.
With the reduction of dimensions of components at 0.1 micron and
below, new physical effects come into play as the standard simulators
of two dimensions (2D) do not consider. In fact the third dimension
comes into play because the transverse and longitudinal dimensions
of the components are of the same order of magnitude. To describe
the operation of such components with greater fidelity, we must
refine simulation tools and adapted to take into account these
phenomena. After an analytical study of the static characteristics of
the component, according to the different operating modes, a
numerical simulation is performed of field-effect transistor with
submicron gate MESFET GaInP. The influence of the dimensions of
the gate length is studied. The results are used to determine the
optimal geometric and physical parameters of the component for their
specific applications and uses.
Abstract: to simulate the phenomenon of electronic transport in semiconductors, we try to adapt a numerical method, often and most frequently it’s that of Monte Carlo. In our work, we applied this method in the case of a ternary alloy semiconductor GaInP in its cubic form; The Calculations are made using a non-parabolic effective-mass energy band model. We consider a band of conduction to three valleys (ΓLX), major of the scattering mechanisms are taken into account in this modeling, as the interactions with the acoustic phonons (elastic collisions) and optics (inelastic collisions). The polar optical phonons cause anisotropic collisions, intra-valleys, very probable in the III-V semiconductors. Other optical phonons, no polar, allow transitions inter-valleys. Initially, we present the full results obtained by the simulation of Monte Carlo in GaInP in stationary regime. We consider thereafter the effects related to the application of an electric field varying according to time, we thus study the transient phenomenon which make their appearance in ternary material
Abstract: The integrity and issues related to electrostatic performance associated with scaling Si MOSFET bulk sub 10nm channel length promotes research in new device architectures such as SOI, double gate and GAA MOSFET. In this paper, we present some novel characteristic of horizontal rectangular gate\gate all around MOSFETs with dual metal of gate we obtained using SILVACO TCAD tools. We will also exhibit some simulation results we obtained relating to the influence of some parameters variation on our structure, that having a direct impact on their threshold voltage and drain current. In addition, our TFET showed reasonable ION/IOFF ratio of (104) and low drain induced barrier lowering (DIBL) of 39 mV/V.