Abstract: Single phase transmission lines are used to transfer data or energy between two users. Transient conditions such as switching operations and short circuit faults cause the generation of the fluctuation on the waveform to be transmitted. Spatial voltage distribution on the single phase transmission line may change owing to the position and duration of the short circuit fault in the system. In this paper, the state space representation of the single phase transmission line for short circuit fault and for various types of terminations is given. Since the transmission line is modeled in time domain using distributed parametric elements, the mathematical representation of the event is given in state space (time domain) differential equation form. It also makes easy to solve the problem because of the time and space dependent characteristics of the voltage variations on the distributed parametrically modeled transmission line.
Abstract: Test data compression is an efficient method for reducing the test application cost. The problem of reducing test data has been addressed by researchers in three different aspects: Test Data Compression, Built-in-Self-Test (BIST) and Test set compaction. The latter two methods are capable of enhancing fault coverage with cost of hardware overhead. The drawback of the conventional methods is that they are capable of reducing the test storage and test power but when test data have redundant length of runs, no additional compression method is followed. This paper presents a modified Run Length Coding (RLC) technique with Multilevel Selective Huffman Coding (MLSHC) technique to reduce test data volume, test pattern delivery time and power dissipation in scan test applications where redundant length of runs is encountered then the preceding run symbol is replaced with tiny codeword. Experimental results show that the presented method not only improves the test data compression but also reduces the overall test data volume compared to recent schemes. Experiments for the six largest ISCAS-98 benchmarks show that our method outperforms most known techniques.
Abstract: An active islanding detection method using disturbance signal injection with intelligent controller is proposed in this study. First, a DC\AC power inverter is emulated in the distributed generator (DG) system to implement the tracking control of active power, reactive power outputs and the islanding detection. The proposed active islanding detection method is based on injecting a disturbance signal into the power inverter system through the d-axis current which leads to a frequency deviation at the terminal of the RLC load when the utility power is disconnected. Moreover, in order to improve the transient and steady-state responses of the active power and reactive power outputs of the power inverter, and to further improve the performance of the islanding detection method, two probabilistic fuzzy neural networks (PFNN) are adopted to replace the traditional proportional-integral (PI) controllers for the tracking control and the islanding detection. Furthermore, the network structure and the online learning algorithm of the PFNN are introduced in detail. Finally, the feasibility and effectiveness of the tracking control and the proposed active islanding detection method are verified with experimental results.
Abstract: Bottom ash from Municipal Solid Waste Incineration
(MSWI) can be viewed as a typical granular material because these
industrial by-products result from the incineration of various
domestic wastes. MSWI bottom ash is mainly used in road
engineering in substitution of the traditional natural aggregates. As
the characterization of their mechanical behavior is essential in order
to use them, specific studies have been led over the past few years. In
the first part of this paper, the mechanical behavior of MSWI bottom
ash is studied with triaxial tests. After, analysis of the experiment
results, the simulation of triaxial tests is carried out by using the
software package CESAR-LCPC. As the first approach in modeling
of this new class material, the Mohr-Coulomb model was chosen to
describe the evolution of material under the influence of external
mechanical actions.
Abstract: Today’s VLSI networks demands for high speed. And
in this work the compact form mathematical model for current mode
signalling in VLSI interconnects is presented.RLC interconnect line
is modelled using characteristic impedance of transmission line and
inductive effect. The on-chip inductance effect is dominant at lower
technology node is emulated into an equivalent resistance. First order
transfer function is designed using finite difference equation, Laplace
transform and by applying the boundary conditions at the source and
load termination. It has been observed that the dominant pole
determines system response and delay in the proposed model. The
novel proposed current mode model shows superior performance as
compared to voltage mode signalling. Analysis shows that current
mode signalling in VLSI interconnects provides 2.8 times better
delay performance than voltage mode. Secondly the damping factor
of a lumped RLC circuit is shown to be a useful figure of merit.
Abstract: Novel compact expressions for propagation constant (γ) of SWCNT and bundled SWCNTs interconnect, in terms of physical parameters such as length, operating frequency and diameter of CNTs is proposed in this work. These simplified expressions enable physical insight and accurate estimation of signal attenuation level and its phase change at any length for a particular frequency. The proposed expressions are validated against SPICE simulated results of lumped as well as distributed equivalent electrical RLC nets of CNT interconnect. These expressions also help us to evaluate the cut off frequencies of SWCNTs for different interconnect lengths.
Abstract: Accurate modeling of high speed RLC interconnects
has become a necessity to address signal integrity issues in current
VLSI design. To accurately model a dispersive system of interconnects
at higher frequencies; a full-wave analysis is required.
However, conventional circuit simulation of interconnects with full
wave models is extremely CPU expensive. We present an algorithm
for reducing large VLSI circuits to much smaller ones with similar
input-output behavior. A key feature of our method, called Frequency
Shift Technique, is that it is capable of reducing linear time-varying
systems. This enables it to capture frequency-translation and sampling
behavior, important in communication subsystems such as mixers,
RF components and switched-capacitor filters. Reduction is obtained
by projecting the original system described by linear differential
equations into a lower dimension. Experiments have been carried out
using Cadence Design Simulator cwhich indicates that the proposed
technique achieves more % reduction with less CPU time than the
other model order reduction techniques existing in literature. We
also present applications to RF circuit subsystems, obtaining size
reductions and evaluation speedups of orders of magnitude with
insignificant loss of accuracy.
Abstract: The resistive-inductive-capacitive behavior of long
interconnects which are driven by CMOS gates are presented in this
paper. The analysis is based on the ¤Ç-model of a RLC load and is
developed for submicron devices. Accurate and analytical
expressions for the output load voltage, the propagation delay and the
short circuit power dissipation have been proposed after solving a
system of differential equations which accurately describe the
behavior of the circuit. The effect of coupling capacitance between
input and output and the short circuit current on these performance
parameters are also incorporated in the proposed model. The
estimated proposed delay and short circuit power dissipation are in
very good agreement with the SPICE simulation with average
relative error less than 6%.
Abstract: This work proposes an accurate crosstalk noise estimation method in the presence of multiple RLC lines for the use in design automation tools. This method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveforms. Noise peak and width expressions have been derived. The results obtained are at good agreement with SPICE results. Results show that average error for noise peak is 4.7% and for the width is 6.15% while allowing a very fast analysis.
Abstract: Timing driven physical design, synthesis, and
optimization tools need efficient closed-form delay models for
estimating the delay associated with each net in an integrated circuit
(IC) design. The total number of nets in a modern IC design has
increased dramatically and exceeded millions. Therefore efficient
modeling of interconnection is needed for high speed IC-s. This
paper presents closed–form expressions for RC and RLC
interconnection trees in current mode signaling, which can be
implemented in VLSI design tool. These analytical model
expressions can be used for accurate calculation of delay after the
design clock tree has been laid out and the design is fully routed.
Evaluation of these analytical models is several orders of magnitude
faster than simulation using SPICE.
Abstract: Fast delay estimation methods, as opposed to
simulation techniques, are needed for incremental performance
driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock
speed and circuit complexity. Inductance causes noise in signal
waveforms, which can adversely affect the performance of the circuit
and signal integrity. Several approaches have been put forward which
consider the inductance for on-chip interconnect modelling. But for
even much higher frequency, of the order of few GHz, the shunt
dielectric lossy component has become comparable to that of other
electrical parameters for high speed VLSI design. In order to cope up
with this effect, on-chip interconnect has to be modelled as
distributed RLCG line. Elmore delay based methods, although
efficient, cannot accurately estimate the delay for RLCG interconnect
line. In this paper, an accurate analytical delay model has been
derived, based on first and second moments of RLCG
interconnection lines. The proposed model considers both the effect
of inductance and conductance matrices. We have performed the
simulation in 0.18μm technology node and an error of as low as less
as 5% has been achieved with the proposed model when compared to
SPICE. The importance of the conductance matrices in interconnect
modelling has also been discussed and it is shown that if G is
neglected for interconnect line modelling, then it will result an delay
error of as high as 6% when compared to SPICE.