Abstract: A 1.2 V, 0.61 mA bias current, low noise amplifier
(LNA) suitable for low-power applications in the 2.4 GHz band is
presented. Circuit has been implemented, laid out and simulated using
a UMC 130 nm RF-CMOS process. The amplifier provides a 13.3 dB
power gain a noise figure NF< 2.28 dB and a 1-dB compression point
of -15.69 dBm, while dissipating 0.74 mW. Such performance make
this design suitable for wireless sensor networks applications such as
ZigBee.
Abstract: This paper describes a low-power second-order filter
for a continuous-time chopper stabilized capacitive sensor interface,
integrated with a fully differential post-CMOS surface-micromachined
MEMS pressure sensor. The circuit uses a single-ended
folded-cascode operational amplifier and two GM-C filters connected
in cascade. The circuit is realized in a 0.18 μm CMOS process and
offers differential to single-ended conversion. The novelty of the
scheme is the cascade of two GM-C filters to achieve a second-order
filter while minimizing power dissipation. The simulated filter cutoff
frequency is 1.14 kHz at common-mode voltage 1.65 V,
operating from a 3.3 V supply while dissipating 172μW of power.
The filter achieves an operating range of 1V for an output load of
1MOhm and 10pF.
Abstract: This work aims to reduce the read power consumption
as well as to enhance the stability of the SRAM cell during the read
operation. A new 10-transisor cell is proposed with a new read
scheme to minimize the power consumption within the memory core.
It has separate read and write ports, thus cell read stability is
significantly improved. A 16Kb SRAM macro operating at 1V
supply voltage is demonstrated in 65 nm CMOS process. Its read
power consumption is reduced to 24% of the conventional design.
The new cell also has lower leakage current due to its special bit-line
pre-charge scheme. As a result, it is suitable for low-power mobile
applications where power supply is restricted by the battery.
Abstract: This paper presents a low-voltage low-power differential linear transconductor with near rail-to-rail input swing. Based on the current-mirror OTA topology, the proposed transconductor combines the Flipped Voltage Follower (FVF) technique to linearize the transconductor behavior that leads to class- AB linear operation and the virtual transistor technique to lower the effective threshold voltages of the transistors which offers an advantage in terms of low supply requirement. Design of the OTA has been discussed. It operates at supply voltages of about ±0.8V. Simulation results for 0.18μm TSMC CMOS technology show a good input range of 1Vpp with a high DC gain of 81.53dB and a total harmonic distortion of -40dB at 1MHz for an input of 1Vpp. The main aim of this paper is to present and compare new OTA design with high transconductance, which has a potential to be used in low voltage applications.
Abstract: The world of wireless telecommunications is rapidly evolving. Technologies under research and development promise to deliver more services to more users in less time. This paper presents the emerging technologies helping wireless systems grow from where we are today into our visions of the future. This paper will cover the applications and characteristics of emerging wireless technologies: Wireless Local Area Networks (WiFi-802.11n), Wireless Personal Area Networks (ZigBee) and Wireless Metropolitan Area Networks (WiMAX). The purpose of this paper is to explain the impending 802.11n standard and how it will enable WLANs to support emerging media-rich applications. The paper will also detail how 802.11n compares with existing WLAN standards and offer strategies for users considering higher-bandwidth alternatives. The emerging IEEE 802.15.4 (ZigBee) standard aims to provide low data rate wireless communications with high-precision ranging and localization, by employing UWB technologies for a low-power and low cost solution. WiMAX (Worldwide Interoperability for Microwave Access) is a standard for wireless data transmission covering a range similar to cellular phone towers. With high performance in both distance and throughput, WiMAX technology could be a boon to current Internet providers seeking to become the leader of next generation wireless Internet access. This paper also explores how these emerging technologies differ from one another.
Abstract: This paper describes a 2.4 GHz passive switch mixer
and a 5/2.5 GHz voltage-controlled negative Gm oscillator (VCO)
with an inversion-mode MOS varactor. Both circuits are implemented
using a 1P8M 0.13 μm process. The switch mixer has an input
referred 1 dB compression point of -3.89 dBm and a conversion
gain of -0.96 dB when the local oscillator power is +2.5 dBm.
The VCO consumes only 1.75 mW, while drawing 1.45 mA from a
1.2 V supply voltage. In order to reduce the passives size, the VCO
natural oscillation frequency is 5 GHz. A clocked CMOS divideby-
two circuit is used for frequency division and quadrature phase
generation. The VCO has a -109 dBc/Hz phase noise at 1 MHz
frequency offset and a 2.35-2.5 GHz tuning range (after the frequency
division), thus complying with ZigBee requirements.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: Wireless Sensor Networks (WSN) are emerging
because of the developments in wireless communication technology and miniaturization of the hardware. WSN consists of a large number of low-cost, low-power, multifunctional sensor nodes to monitor physical conditions, such as temperature, sound, vibration, pressure,
motion, etc. The MAC protocol to be used in the sensor networks must be energy efficient and this should aim at conserving the energy during its operation. In this paper, with the focus of analyzing the
MAC protocols used in wireless Adhoc networks to WSN, simulation
experiments were conducted in Global Mobile Simulator
(GloMoSim) software. Number of packets sent by regular nodes, and received by sink node in different deployment strategies, total energy
spent, and the network life time have been chosen as the metric for comparison. From the results of simulation, it is evident that the IEEE 802.11 protocol performs better compared to CSMA and MACA protocols.
Abstract: With rapid technology scaling, the proportion of the
static power consumption catches up with dynamic power
consumption gradually. To decrease leakage consumption is
becoming more and more important in low-power design. This paper
presents a power-gating scheme for P-DTGAL (p-type dual
transmission gate adiabatic logic) circuits to reduce leakage power
dissipations under deep submicron process. The energy dissipations of
P-DTGAL circuits with power-gating scheme are investigated in
different processes, frequencies and active ratios. BSIM4 model is
adopted to reflect the characteristics of the leakage currents. HSPICE
simulations show that the leakage loss is greatly reduced by using the
P-DTGAL with power-gating techniques.
Abstract: The proposed multiplexer-based novel 1-bit full
adder cell is schematized by using DSCH2 and its layout is generated
by using microwind VLSI CAD tool. The adder cell layout
interconnect analysis is performed by using BSIM4 layout analyzer.
The adder circuit is compared with other six existing adder circuits
for parametric analysis. The proposed adder cell gives better
performance than the other existing six adder circuits in terms of
power, propagation delay and PDP. The proposed adder circuit is
further analyzed for interconnect analysis, which gives better
performance than other adder circuits in terms of layout thickness,
width and height.
Abstract: In this paper, the implementation of low power,
high throughput convolutional filters for the one dimensional
Discrete Wavelet Transform and its inverse are presented. The
analysis filters have already been used for the implementation of a
high performance DWT encoder [15] with minimum memory
requirements for the JPEG 2000 standard. This paper presents the
design techniques and the implementation of the convolutional filters
included in the JPEG2000 standard for the forward and inverse DWT
for achieving low-power operation, high performance and reduced
memory accesses. Moreover, they have the ability of performing
progressive computations so as to minimize the buffering between
the decomposition and reconstruction phases. The experimental
results illustrate the filters- low power high throughput characteristics
as well as their memory efficient operation.
Abstract: Parallel Prefix addition is a technique for improving
the speed of binary addition. Due to continuing integrating intensity
and the growing needs of portable devices, low-power and highperformance
designs are of prime importance. The classical parallel
prefix adder structures presented in the literature over the years
optimize for logic depth, area, fan-out and interconnect count of logic
circuits. In this paper, a new architecture for performing 8-bit, 16-bit
and 32-bit Parallel Prefix addition is proposed. The proposed prefix
adder structures is compared with several classical adders of same
bit width in terms of power, delay and number of computational
nodes. The results reveal that the proposed structures have the least
power delay product when compared with its peer existing Prefix
adder structures. Tanner EDA tool was used for simulating the adder
designs in the TSMC 180 nm and TSMC 130 nm technologies.
Abstract: A wrist-band type biosignal measurement system and its data transfer through human body communication (HBC) were investigated. An HBC method based on pulses of ultra-wide band instead of using frequency or amplitude modulations was studied and implemented since the system became very compact and it was more suited for personal or mobile health monitoring. Our system measured photo-plethysmogram (PPG) and measured PPG signals were transmitted through a finger to a monitoring PC system. The device was compact and low-power consuming. HBC communication has very strongsecurity measures since it does not use wireless network.Furthermore, biosignal monitoring system becomes handy because it does not need to have wire connections.
Abstract: Ultra-low-power (ULP) circuits have received
widespread attention due to the rapid growth of biomedical
applications and Battery-less Electronics. Subthreshold region of
transistor operation is used in ULP circuits. Major research challenge
in the subthreshold operating region is to extract the ULP benefits
with minimal degradation in speed and robustness. Process, Voltage
and Temperature (PVT) variations significantly affect the
performance of subthreshold circuits. Designed performance
parameters of ULP circuits may vary largely due to temperature
variations. Hence, this paper investigates the effect of temperature
variation on device and circuit performance parameters at different
biasing voltages in the subthreshold region. Simulation results clearly
demonstrate that in deep subthreshold and near threshold voltage
regions, performance parameters are significantly affected whereas in
moderate subthreshold region, subthreshold circuits are more
immune to temperature variations. This establishes that moderate
subthreshold region is ideal for temperature immune circuits.
Abstract: This paper describes a low-voltage and low-power
channel selection analog front end with continuous-time low pass
filters and highly linear programmable gain amplifier (PGA). The
filters were realized as balanced Gm-C biquadratic filters to achieve a
low current consumption. High linearity and a constant wide
bandwidth are achieved by using a new transconductance (Gm) cell.
The PGA has a voltage gain varying from 0 to 65dB, while
maintaining a constant bandwidth. A filter tuning circuit that requires
an accurate time base but no external components is presented.
With a 1-Vrms differential input and output, the filter achieves
-85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA
were implemented in a 0.18um 1P6M n-well CMOS process. They
consume 3.2mW from a 1.8V power supply and occupy an area of
0.19mm2.
Abstract: A direct downconversion receiver implemented in 0.13 μm 1P8M process is presented. The circuit is formed by a single-end LNA, an active balun for conversion into balanced mode, a quadrature double-balanced passive switch mixer and a quadrature voltage-controlled oscillator. The receiver operates in the 2.4 GHz ISM band and complies with IEEE 802.15.4 (ZigBee) specifications. The circuit exhibits a very low noise figure of only 2.27 dB and dissipates only 14.6 mW with a 1.2 V supply voltage and is hence suitable for low-power applications.
Abstract: This paper studies a vital issue in wireless
communications, which is the transmission of images over Wireless
Personal Area Networks (WPANs) through the Bluetooth network. It
presents a simple method to improve the efficiency of error control
code of old Bluetooth versions over mobile WPANs through
Interleaved Error Control Code (IECC) technique. The encoded
packets are interleaved by simple block interleaver. Also, the paper
presents a chaotic interleaving scheme as a tool against bursts of
errors which depends on the chaotic Baker map. Also, the paper
proposes using the chaotic interleaver instead of traditional block
interleaver with Forward Error Control (FEC) scheme. A comparison
study between the proposed and standard techniques for image
transmission over a correlated fading channel is presented.
Simulation results reveal the superiority of the proposed chaotic
interleaving scheme to other schemes. Also, the superiority of FEC
with proposed chaotic interleaver to the conventional interleavers
with enhancing the security level with chaotic interleaving packetby-
packet basis.
Abstract: In this study, we introduced a communication system
where human body was used as medium through which data were
transferred. Multiple biosignal sensing units were attached to a subject
and wireless personal area network was formed. Data of the sensing
units were shared among them. We used wideband pulse
communication that was simple, low-power consuming and high data
rated. Each unit functioned as independent communication device or
node. A method of channel search and communication among the
modes was developed. A protocol of carrier sense multiple
access/collision detect was implemented in order to avoid data
collision or interferences. Biosignal sensing units should be located at
different locations due to the nature of biosignal origin. Our research
provided a flexibility of collecting data without using electrical wires.
More non-constrained measurement was accomplished which was
more suitable for u-Health monitoring.
Abstract: Versatile dual-mode class-AB CMOS four-quadrant
analog multiplier circuit is presented. The dual translinear loops and
current mirrors are the basic building blocks in realization scheme.
This technique provides; wide dynamic range, wide-bandwidth response
and low power consumption. The major advantages of this
approach are; its has single ended inputs; since its input is dual translinear
loop operate in class-AB mode which make this multiplier
configuration interesting for low-power applications; current multiplying,
voltage multiplying, or current and voltage multiplying can
be obtainable with balanced input. The simulation results of versatile
analog multiplier demonstrate a linearity error of 1.2 %, a -3dB bandwidth
of about 19MHz, a maximum power consumption of 0.46mW,
and temperature compensated. Operation of versatile analog multiplier
was also confirmed through an experiment using CMOS transistor
array.
Abstract: We demonstrate a 1×4 coarse wavelength
division-multiplexing (CWDM) planar concave grating
multiplexer/demultiplexer and its application in re-configurable
optical add/drop multiplexer (ROADM) system in silicon-on-insulator
substrate. The wavelengths of the demonstrated concave grating
multiplexer align well with the ITU-T standard. We demonstrate a
prototype of ROADM comprising two such concave gratings and four
wide-band thermo-optical MZI switches. Undercut technology which
removes the underneath silicon substrate is adopted in optical switches
in order to minimize the operation power. For all the thermal heaters,
the operation voltage is smaller than 1.5 V, and the switch power is
~2.4 mW. High throughput pseudorandom binary sequence (PRBS)
data transmission with up to 100 Gb/s is demonstrated, showing the
high-performance ROADM functionality.