Design of a CMOS Highly Linear Front-end IC with Auto Gain Controller for a Magnetic Field Transceiver
This paper describes a low-voltage and low-power
channel selection analog front end with continuous-time low pass
filters and highly linear programmable gain amplifier (PGA). The
filters were realized as balanced Gm-C biquadratic filters to achieve a
low current consumption. High linearity and a constant wide
bandwidth are achieved by using a new transconductance (Gm) cell.
The PGA has a voltage gain varying from 0 to 65dB, while
maintaining a constant bandwidth. A filter tuning circuit that requires
an accurate time base but no external components is presented.
With a 1-Vrms differential input and output, the filter achieves
-85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA
were implemented in a 0.18um 1P6M n-well CMOS process. They
consume 3.2mW from a 1.8V power supply and occupy an area of
0.19mm2.
[1] Pilsoon Choi et.al, "An Experimental Coin-Sized Radio for Extremely
Low-Power WPAN Application at 2.4GHz," IEEE J. Solid-State Circuits,
vol. 38, no.12, pp. 2258~2268, Dec. 2003.
[2] C. Cojocaru et.al, "A 43mW Bluetooth transceiver with -91dBm
sensitivity," ISSCC Dig. Tech. Papers, pp. 90~91, Feb. 2003.
[3] IEEE Computer Society, "IEEE Standard for Part 15.4: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) specifications for Low
Rate Wireless Personal Area Networks (LR-WPANs)", IEEE Std
802.15.4TM-2003.
[4] Mario Valla et.al, "A 72-mW CMOS 802.11a Direct Conversion
Front-End With 3.5-dB NF and 200-kHz 1/f Noise Corner," IEEE J.
Solid-State Circuits, vol. 40, no.4, pp. 970~977, April 2005.
[5] Angelika Schneider et.al, "Nonlinear Analysis of Noise in
Current-Steering Variable Gain Amplifiers," IEEE J. Solid-State Circuits,
vol. 39, no.2, pp. 290~296, Feb. 2004.
[6] Jose Silva-Martinez et.al, "A 10.7-MHz 68-dB SNR CMOS
Continuous-Time Filter with On-Chip Automatic Tunig," IEEE J.
Solid-State Circuits, vol. 27, no.12, pp.1843~1853, Dec. 1992.
[7] Yorgos palaskas et.al, "A "Divide and Conquer" Technique for
Implementing Wide Dynamic Range Continuous-Time Filters," IEEE J.
Solid-State Circuits, vol. 39, no.2, pp.297~307, Feb. 2004.
[1] Pilsoon Choi et.al, "An Experimental Coin-Sized Radio for Extremely
Low-Power WPAN Application at 2.4GHz," IEEE J. Solid-State Circuits,
vol. 38, no.12, pp. 2258~2268, Dec. 2003.
[2] C. Cojocaru et.al, "A 43mW Bluetooth transceiver with -91dBm
sensitivity," ISSCC Dig. Tech. Papers, pp. 90~91, Feb. 2003.
[3] IEEE Computer Society, "IEEE Standard for Part 15.4: Wireless Medium
Access Control (MAC) and Physical Layer (PHY) specifications for Low
Rate Wireless Personal Area Networks (LR-WPANs)", IEEE Std
802.15.4TM-2003.
[4] Mario Valla et.al, "A 72-mW CMOS 802.11a Direct Conversion
Front-End With 3.5-dB NF and 200-kHz 1/f Noise Corner," IEEE J.
Solid-State Circuits, vol. 40, no.4, pp. 970~977, April 2005.
[5] Angelika Schneider et.al, "Nonlinear Analysis of Noise in
Current-Steering Variable Gain Amplifiers," IEEE J. Solid-State Circuits,
vol. 39, no.2, pp. 290~296, Feb. 2004.
[6] Jose Silva-Martinez et.al, "A 10.7-MHz 68-dB SNR CMOS
Continuous-Time Filter with On-Chip Automatic Tunig," IEEE J.
Solid-State Circuits, vol. 27, no.12, pp.1843~1853, Dec. 1992.
[7] Yorgos palaskas et.al, "A "Divide and Conquer" Technique for
Implementing Wide Dynamic Range Continuous-Time Filters," IEEE J.
Solid-State Circuits, vol. 39, no.2, pp.297~307, Feb. 2004.
@article{"International Journal of Electrical, Electronic and Communication Sciences:51646", author = "Yeon-kug Moon and Kang-Yoon Lee and Yun-Jae Won and Seung-Ok Lim", title = "Design of a CMOS Highly Linear Front-end IC with Auto Gain Controller for a Magnetic Field Transceiver", abstract = "This paper describes a low-voltage and low-power
channel selection analog front end with continuous-time low pass
filters and highly linear programmable gain amplifier (PGA). The
filters were realized as balanced Gm-C biquadratic filters to achieve a
low current consumption. High linearity and a constant wide
bandwidth are achieved by using a new transconductance (Gm) cell.
The PGA has a voltage gain varying from 0 to 65dB, while
maintaining a constant bandwidth. A filter tuning circuit that requires
an accurate time base but no external components is presented.
With a 1-Vrms differential input and output, the filter achieves
-85dB THD and a 78dB signal-to-noise ratio. Both the filter and PGA
were implemented in a 0.18um 1P6M n-well CMOS process. They
consume 3.2mW from a 1.8V power supply and occupy an area of
0.19mm2.", keywords = "component ; Channel selection filters, DC offset,programmable gain amplifier, tuning circuit", volume = "5", number = "7", pages = "797-5", }