Abstract: Fast forecasting of stock market prices is very important for
strategic planning. In this paper, a new approach for fast forecasting of
stock market prices is presented. Such algorithm uses new high speed
time delay neural networks (HSTDNNs). The operation of these
networks relies on performing cross correlation in the frequency
domain between the input data and the input weights of neural
networks. It is proved mathematically and practically that the number
of computation steps required for the presented HSTDNNs is less
than that needed by traditional time delay neural networks
(TTDNNs). Simulation results using MATLAB confirm the
theoretical computations.
Abstract: In this paper, we present a simple circuit for
Manchester decoding and without using any complicated or
programmable devices. This circuit can decode 90kbps of transmitted
encoded data; however, greater than this transmission rate can be
decoded if high speed devices were used. We also present a new
method for extracting the embedded clock from Manchester data in
order to use it for serial-to-parallel conversion. All of our
experimental measurements have been done using simulation.
Abstract: The evolution of technology and construction techniques has enabled the upgrading of transport networks. In particular, the high-speed rail networks allow convoys to peak at above 300 km/h. These structures, however, often significantly impact the surrounding environment. Among the effects of greater importance are the ones provoked by the soundwave connected to train transit. The wave propagation affects the quality of life in areas surrounding the tracks, often for several hundred metres. There are substantial damages to properties (buildings and land), in terms of market depreciation. The present study, integrating expertise in acoustics, computering and evaluation fields, outlines a useful model to select project paths so as to minimize the noise impact and reduce the causes of possible litigation. It also facilitates the rational selection of initiatives to contain the environmental damage to the already existing railway tracks. The research is developed with reference to the Italian regulatory framework (usually more stringent than European and international standards) and refers to a case study concerning the high speed network in Italy.
Abstract: This paper describes the design and fabrication of a clock and data recovery circuit (CDR). We propose a new clock and data recovery which is based on a 1/4-rate frequency detector (QRFD). The proposed frequency detector helps reduce the VCO frequency and is thus advantageous for high speed application. The proposed frequency detector can achieve low jitter operation and extend the pull-in range without using the reference clock. The proposed CDR was implemented using a 1/4-rate bang-bang type phase detector (PD) and a ring voltage controlled oscillator (VCO). The CDR circuit has been fabricated in a standard 0.18 CMOS technology. It occupies an active area of 1 x 1 and consumes 90 mW from a single 1.8V supply.
Abstract: A fully on-chip low drop-out (LDO) voltage regulator with 100pF output load capacitor is presented. A novel frequency compensation scheme using current buffer is adopted to realize single dominant pole within the unit gain frequency of the regulation loop, the phase margin (PM) is at least 50 degree under the full range of the load current, and the power supply rejection (PSR) character is improved compared with conventional Miller compensation. Besides, the differentiator provides a high speed path during the load current transient. Implemented in 0.18μm CMOS technology, the LDO voltage regulator provides 100mA load current with a stable 1.8V output voltage consuming 80μA quiescent current.
Abstract: In this paper we present two novel 1-bit full adder
cells in dynamic logic style. NP-CMOS (Zipper) and Multi-Output
structures are used to design the adder blocks. Characteristic of
dynamic logic leads to higher speeds than the other standard static
full adder cells. Using HSpice and 0.18┬Ám CMOS technology
exhibits a significant decrease in the cell delay which can result in a
considerable reduction in the power-delay product (PDP). The PDP
of Multi-Output design at 1.8v power supply is around 0.15 femto
joule that is 5% lower than conventional dynamic full adder cell and
at least 21% lower than other static full adders.
Abstract: Phase locked loops for data links operating at 10 Gb/s
or faster are low phase noise devices designed to operate with a low
jitter reference clock. Characterization of their jitter transfer function
is difficult because the intrinsic noise of the device is comparable to
the random noise level in the reference clock signal. A linear model
is proposed to account for the intrinsic noise of a PLL. The intrinsic
noise data of a PLL for 10 Gb/s links is presented. The jitter transfer
function of a PLL in a test chip for 12.8 Gb/s data links was
determined in experiments using the 400 MHz reference clock as the
source of simultaneous excitations over a wide range of frequency.
The result shows that the PLL jitter transfer function can be
approximated by a second order linear model.
Abstract: The technology usages of high speed Internet leads to
establish and start new era of online education. With the
advancement of the information technology and communication
systems new opportunities have been created. This leads universities
to have various online education channels to meet the demand of
different learners- needs. One of these channels is M-learning, which
can be used to improve the online education environment. With using
such mobile technology in learning both students and instructors can
easily access educational courses anytime from anywhere. The paper
first presents literature about mobile learning and to what extent this
approach can be utilized to enhance the overall learning system. It
provides a comparison between mobile learning and traditional elearning
showing the wide array of benefits of the new generation of
technology. The possible challenges and potential advantages of Mlearning
in the online education system are also discussed.
Abstract: 4G Communication Networks provide heterogeneous
wireless technologies to mobile subscribers through IP based
networks and users can avail high speed access while roaming across
multiple wireless channels; possible by an organized way to manage
the Quality of Service (QoS) functionalities in these networks. This
paper proposes the idea of developing a novel QoS optimization
architecture that will judge the user requirements and knowing peak
times of services utilization can save the bandwidth/cost factors. The
proposed architecture can be customized according to the network
usage priorities so as to considerably improve a network-s QoS
performance.
Abstract: The designing of charge pump with high gain Op-
Amp is a challenging task for getting faithful response .Design of
high performance phase locked loop require ,a design of high
performance charge pump .We have designed a operational amplifier
for reducing the error caused by high speed glitch in a transistor and
mismatch currents . A separate Op-Amp has designed in 180 nm
CMOS technology by CADENCE VIRTUOSO tool. This paper
describes the design of high performance charge pump for GHz
CMOS PLL targeting orthogonal frequency division multiplexing
(OFDM) application. A high speed low power consumption Op-Amp
with more than 500 MHz bandwidth has designed for increasing the
speed of charge pump in Phase locked loop.
Abstract: Chatter vibration has been a troublesome problem for a
machine tool toward the high precision and high speed machining.
Essentially, the machining performance is determined by the dynamic
characteristics of the machine tool structure and dynamics of cutting
process. Therefore the dynamic vibration behavior of spindle tool
system greatly determines the performance of machine tool. The
purpose of this study is to investigate the influences of the machine
frame structure on the dynamic frequency of spindle tool unit through
finite element modeling approach. To this end, a realistic finite
element model of the vertical milling system was created by
incorporated the spindle-bearing model into the spindle head stock of
the machine frame. Using this model, the dynamic characteristics of
the milling machines with different structural designs of spindle head
stock and identical spindle tool unit were demonstrated. The results of
the finite element modeling reveal that the spindle tool unit behaves
more compliant when the excited frequency approaches the natural
mode of the spindle tool; while the spindle tool show a higher dynamic
stiffness at lower frequency that may be initiated by the structural
mode of milling head. Under this condition, it is concluded that the
structural configuration of spindle head stock associated with the
vertical column of milling machine plays an important role in
determining the machining dynamics of the spindle unit.
Abstract: Vehicle which are turning or maneuvering at high speeds
are susceptible to sliding and subsequently deviate from desired path. In
this paper the dynamics governing the Yaw/Roll behavior of a vehicle
has been simulated. Two different simulations have been used one for
the real vehicle, for which a fuzzy controller is designed to increase its
directional stability property. The other simulation is for a hypothetical
vehicle with much higher tire cornering stiffness which is capable of
developing the required lateral forces at the tire-ground patch contact to
attain the desired lateral acceleration for the vehicle to follow the
desired path without slippage. This simulation model is our reference
model.
The logic for keeping the vehicle on the desired track in the cornering
or maneuvering state is to have some braking forces on the inner or
outer tires based on the direction of vehicle deviation from the desired
path. The inputs to our vehicle simulation model is steer angle δ and
vehicle velocity V , and the outputs can be any kinematical parameters
like yaw rate, yaw acceleration, side slip angle, rate of side slip angle
and so on. The proposed fuzzy controller is a feed forward controller.
This controller has two inputs which are steer angle δ and vehicle
velocity V, and the output of the controller is the correcting moment M,
which guides the vehicle back to the desired track. To develop the
membership functions for the controller inputs and output and the fuzzy
rules, the vehicle simulation has been run for 1000 times and the
correcting moment have been determined by trial and error. Results of
the vehicle simulation with fuzzy controller are very promising
and show the vehicle performance is enhanced greatly over the
vehicle without the controller. In fact the vehicle performance
with the controller is very near the performance of the reference
ideal model.
Abstract: LABVIEW is a graphical programming language that has its roots in automation control and data acquisition. In this paper we have utilized this platform to provide a powerful toolset for process identification and control of nonlinear systems based on artificial neural networks (ANN). This tool has been applied to the monitoring and control of a lab-scale distillation column DELTALAB DC-SP. The proposed control scheme offers high speed of response for changes in set points and null stationary error for dual composition control and shows robustness in presence of externally imposed disturbance.
Abstract: This paper analyses the torsional efforts in gas turbine-generator shafts caused by high speed automatic reclosing of transmission lines. This issue is especially important for cases of three phase short circuit and unsuccessful reclosure of lines in the vicinity of the thermal plant. The analysis was carried out for the thermal plant TERMOPERNAMBUCO located on Northeast region of Brazil. It is shown that stress level caused by lines unsuccessful reclosing can be several times higher than terminal three-phase short circuit. Simulations were carried out with detailed shaft torsional model provided by machine manufacturer and with the “Alternative Transient Program – ATP" program [1]. Unsuccessful three phase reclosing for selected lines in the area closed to the plant indicated most critical cases. Also, reclosing first the terminal next to the gas turbine gererator will lead also to the most critical condition. Considering that the values of transient torques are very sensible to the instant of reclosing, simulation of unsuccessful reclosing with statistics ATP switch were carried out for determination of most critical transient torques for each section of the generator turbine shaft.
Abstract: Reno-pin contact test is a method that is controlled by
DC motor used to characterize electronic chips. This method is used in
electronic and telecommunication devices. A new electric
performance testing system is developed in which the testing method
is controlled by using Piezoelectric Transducer (PZT) instead of DC
motor which reduces vibration and noise. The vertical displacement of
the Reno-pin is very short in the Reno-pin contact testing system. Now
using a flexible guide in the new Reno-pin contact system, the vertical
movement of the Reno-pin is increased many times of the existing
Reno-pin contact testing method using DC motor. Using the present
electric performance testing system with a flexible hinge and PZT
instead of DC motor, manufacturing of electronic chips are able to
characterize chips with low cost and high speed.
Abstract: Analytically the effect of polarization dependent loss on a high speed fiber optic communication link has been investigated. PDL and the signal's incoming state of polarization (SOP) have a significant co-relation between them and their various combinations produces different effects on the system behavior which has been inspected. Pauli's spin operator and PDL parameters are combined together to observe the attenuation effect induced by PDL in a link containing multiple PDL elements. It is found that in the presence of PDL the Q-factor and BER at the receiver undergoes fluctuation causing the system to be unstable and results show that it is mainly due to optical-signal-to-parallel-noise ratio (OSNItpar) that these parameters fluctuate. Generally the Q-factor, BER deteriorates as the value of average PDL in the link increases except for depolarized light for which the system parameters improves when PDL increases.
Abstract: The paper proposes the novel design of a 3T XOR gate combining complementary CMOS with pass transistor logic. The design has been compared with earlier proposed 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An eight transistor full adder has been designed using the proposed three-transistor XOR gate and its performance has been investigated using 0.15um and 0.35um technologies. Compared to the earlier designed 10 transistor full adder, the proposed adder shows a significant improvement in silicon area and power delay product. The whole simulation has been carried out using HSPICE.
Abstract: The contribution is dealing with the influence of high speed parameters on the quality of machined surface. In general the principle of high speed cutting lies in achieving faster machine times with concurrent increase in accuracy and quality of the machined areas in largely irregular, mathematically hard to define shapes. High speed machining is a highly effective method of machining with the following goals: increasing of machining productivity, increasing of quality of the machined surface, improving of machining economy, improving of ecological aspects of machining. This article is based on an experiment performed by the Department of Machining and Assembly of the Faculty of Mechanical Engineering of VŠBTechnical University of Ostrava.
Abstract: Orthogonal Frequency Division Multiplexing
(OFDM) is an efficient method of data transmission for high speed
communication systems. However, the main drawback of OFDM
systems is that, it suffers from the problem of high Peak-to-Average
Power Ratio (PAPR) which causes inefficient use of the High Power
Amplifier and could limit transmission efficiency. OFDM consist of
large number of independent subcarriers, as a result of which the
amplitude of such a signal can have high peak values. In this paper,
we propose an effective reduction scheme that combines DCT and
SLM techniques. The scheme is composed of the DCT followed by
the SLM using the Riemann matrix to obtain phase sequences for the
SLM technique. The simulation results show PAPR can be greatly
reduced by applying the proposed scheme. In comparison with
OFDM, while OFDM had high values of PAPR –about 10.4dB our
proposed method achieved about 4.7dB reduction of the PAPR with
low complexities computation. This approach also avoids
randomness in phase sequence selection, which makes it simpler to
decode at the receiver. As an added benefit, the matrices can be
generated at the receiver end to obtain the data signal and hence it is
not required to transmit side information (SI).
Abstract: In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.