Mobility Management Architecture for Transport System

Next generation wireless/mobile networks will be IP based cellular networks integrating the internet with cellular networks. In this paper, we propose a new architecture for a high speed transport system and a mobile management protocol for mobile internet users in a transport system. Existing mobility management protocols (MIPv6, HMIPv6) do not consider real world fast moving wireless hosts (e.g. passengers in a train). For this reason, we define a virtual organization (VO) and proposed the VO architecture for the transport system. We also classify mobility as VO mobility (intra VO) and macro mobility (inter VO). Handoffs in VO are locally managed and transparent to the CH while macro mobility is managed with Mobile IPv6. And, from the features of the transport system, such as fixed route and steady speed, we deduce the movement route and the handoff disruption time of each handoff. To reduce packet loss during handoff disruption time, we propose pre-registration scheme using pre-registration. Moreover, the proposed protocol can eliminate unnecessary binding updates resulting from sequence movement at high speed. The performance evaluations demonstrate our proposed protocol has a good performance at transport system environment. Our proposed protocol can be applied to the usage of wireless internet on the train, subway, and high speed train.

Position Based Routing Protocol with More Reliability in Mobile Ad Hoc Network

Position based routing protocols are the kinds of routing protocols, which they use of nodes location information, instead of links information to routing. In position based routing protocols, it supposed that the packet source node has position information of itself and it's neighbors and packet destination node. Greedy is a very important position based routing protocol. In one of it's kinds, named MFR (Most Forward Within Radius), source node or packet forwarder node, sends packet to one of it's neighbors with most forward progress towards destination node (closest neighbor to destination). Using distance deciding metric in Greedy to forward packet to a neighbor node, is not suitable for all conditions. If closest neighbor to destination node, has high speed, in comparison with source node or intermediate packet forwarder node speed or has very low remained battery power, then packet loss probability is increased. Proposed strategy uses combination of metrics distancevelocity similarity-power, to deciding about giving the packet to which neighbor. Simulation results show that the proposed strategy has lower lost packets average than Greedy, so it has more reliability.

Some Design Issues in Designing of 50KW 50Krpm Permanent Magnet Synchronous Machine

A numbers of important developments have led to an increasing attractiveness for very high speed electrical machines (either motor or generator). Specifically the increasing switching speed of power electronics, high energy magnets, high strength retaining materials, better high speed bearings and improvements in design analysis are the primary drivers in a move to higher speed. The design challenges come in the mechanical design both in terms of strength and resonant modes and in the electromagnetic design particularly in respect of iron losses and ac losses in the various conducting parts including the rotor. This paper describes detailed design work which has been done on a 50,000 rpm, 50kW permanent magnet( PM) synchronous machine. It describes work on electromagnetic and rotor eddy current losses using a variety of methods including both 2D finite element analysis

Analysis of CNT Bundle and its Comparison with Copper for FPGAs Interconnects

Each new semiconductor technology node brings smaller transistors and wires. Although this makes transistors faster, wires get slower. In nano-scale regime, the standard copper (Cu) interconnect will become a major hurdle for FPGA interconnect due to their high resistivity and electromigration. This paper presents the comprehensive evaluation of mixed CNT bundle interconnects and investigates their prospects as energy efficient and high speed interconnect for future FPGA routing architecture. All HSPICE simulations are carried out at operating frequency of 1GHz and it is found that mixed CNT bundle implemented in FPGAs as interconnect can potentially provide a substantial delay and energy reduction over traditional interconnects at 32nm process technology.

Wear Mechanisms in High Speed Steel Gear Cutting Tools

In this paper, the wear of high speed steel hobs during hobbing has been studied. The wear mechanisms are strongly influenced by the choice of cutting speed. At moderate and high cutting speeds three major wear mechanisms were identified: abrasion, mild adhesive and severe adhesive. The microstructure and wear behavior of two high speed steel grades (M2 and ASP30) has been compared. In contrast, a variation in chemical composition or microstructure of HSS tool material generally did not change the dominant wear mechanism. However, the tool material properties determine the resistance against the operating wear mechanism and consequently the tool life. The metallographic analysis and wear measurement at the tip of hob teeth included scanning electron microscopy and stereoscope microscopy. Roughness profilometery is used for measuring the gear surface roughness.

The Suitability of GPS Receivers Update Rates for Navigation Applications

Navigation is the processes of monitoring and controlling the movement of an object from one place to another. Currently, Global Positioning System (GPS) is the main navigation system used all over the world for navigation applications. GPS receiver receives signals from at least three satellites to locate and display itself. Displayed positioning information is updated continuously. Update rate is the number of times per second that a display is illuminated. The speed of update is governed by receiver update rate. A higher update rate decreases display lag time and improves distance measurements and tracking especially when moving on a curvy route. The majority of GPS receivers used nowadays are updated every second continuously. This period is considered reasonable for some applications while it is long relatively for high speed applications. In this paper, the suitability and feasibility of GPS receiver with different update rates will be evaluated for various applications according to the level of speed and update rate needed for particular applications.

A 1.2-ns16×16-Bit Binary Multiplier Using High Speed Compressors

For higher order multiplications, a huge number of adders or compressors are to be used to perform the partial product addition. We have reduced the number of adders by introducing special kind of adders that are capable to add five/six/seven bits per decade. These adders are called compressors. Binary counter property has been merged with the compressor property to develop high order compressors. Uses of these compressors permit the reduction of the vertical critical paths. A 16×16 bit multiplier has been developed using these compressors. These compressors make the multipliers faster as compared to the conventional design that have been used 4-2 compressors and 3-2 compressors.

FPGA Based Parallel Architecture for the Computation of Third-Order Cross Moments

Higher-order Statistics (HOS), also known as cumulants, cross moments and their frequency domain counterparts, known as poly spectra have emerged as a powerful signal processing tool for the synthesis and analysis of signals and systems. Algorithms used for the computation of cross moments are computationally intensive and require high computational speed for real-time applications. For efficiency and high speed, it is often advantageous to realize computation intensive algorithms in hardware. A promising solution that combines high flexibility together with the speed of a traditional hardware is Field Programmable Gate Array (FPGA). In this paper, we present FPGA-based parallel architecture for the computation of third-order cross moments. The proposed design is coded in Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) and functionally verified by implementing it on Xilinx Spartan-3 XC3S2000FG900-4 FPGA. Implementation results are presented and it shows that the proposed design can operate at a maximum frequency of 86.618 MHz.

Dynamic Analyses for Passenger Volume of Domestic Airline and High Speed Rail

Discrete choice model is the most used methodology for studying traveler-s mode choice and demand. However, to calibrate the discrete choice model needs to have plenty of questionnaire survey. In this study, an aggregative model is proposed. The historical data of passenger volumes for high speed rail and domestic civil aviation are employed to calibrate and validate the model. In this study, different models are compared so as to propose the best one. From the results, systematic equations forecast better than single equation do. Models with the external variable, which is oil price, are better than models based on closed system assumption.

The Effect of High-speed Milling on Surface Roughness of Hardened Tool Steel

The objective of this research was to study factors, which were affected on surface roughness in high speed milling of hardened tool steel. Material used in the experiment was tool steel JIS SKD 61 that hardened on 60 ±2 HRC. Full factorial experimental design was conducted on 3 factors and 3 levels (3 3 designs) with 2 replications. Factors were consisted of cutting speed, feed rate, and depth of cut. The results showed that influenced factor affected to surface roughness was cutting speed, feed rate and depth of cut which showed statistical significant. Higher cutting speed would cause on better surface quality. On the other hand, higher feed rate would cause on poorer surface quality. Interaction of factor was found that cutting speed and depth of cut were significantly to surface quality. The interaction of high cutting speed associated with low depth of cut affected to better surface quality than low cutting speed and high depth of cut.

Synthesis and Characterization of PEG-Silane Functionalized Iron Oxide Nanoparticle as MRI T2 Contrast Agent

Iron oxide nanoparticle was synthesized by reactive-precipitation method followed by high speed centrifuge and phase transfer in order to stabilized nanoparticles in the solvent. Particle size of SPIO was 8.2 nm by SEM, and the hydraulic radius was 17.5 nm by dynamic light scattering method. Coercivity and saturated magnetism were determined by VSM (vibrating sample magnetometer), coercivity of nanoparticle was lower than 10 Hc, and the saturated magnetism was higher than 65 emu/g. Stabilized SPIO was then transferred to aqueous phase by reacted with excess amount of poly (ethylene glycol) (PEG) silane. After filtration and dialysis, the SPIO T2 contrast agent was ready to use. The hydraulic radius of final product was about 70~100 nm, the relaxation rates R2 (1/T2) measured by magnetic resonance imaging (MRI) was larger than 200(sec-1).

Multiple Moving Talker Tracking by Integration of Two Successive Algorithms

In this paper, an estimation accuracy of multiple moving talker tracking using a microphone array is improved. The tracking can be achieved by the adaptive method in which two algorithms are integrated, namely, the PAST (Projection Approximation Subspace Tracking) algorithm and the IPLS (Interior Point Least Square) algorithm. When either talker begins to speak again after a silent period, an appropriate feasible region for an evaluation function of the IPLS algorithm might not be set. Then, the tracking fails due to the incorrect updating. Therefore, if an increment of the number of active talkers is detected, the feasible region must be reset. Then, a low cost realization is required for the high speed tracking and a high accuracy realization is desired for the precise tracking. In this paper, the directions roughly estimated using the delayed-sum-array method are used for the resetting. Several results of experiments performed in an actual room environment show the effectiveness of the proposed method.

Image Sensor Matrix High Speed Simulation

This paper presents a new high speed simulation methodology to solve the long simulation time problem of CMOS image sensor matrix. Generally, for integrating the pixel matrix in SOC and simulating the system performance, designers try to model the pixel in various modeling languages such as VHDL-AMS, SystemC or Matlab. We introduce a new alternative method based on spice model in cadence design platform to achieve accuracy and reduce simulation time. The simulation results indicate that the pixel output voltage maximum error is at 0.7812% and time consumption reduces from 2.2 days to 13 minutes achieving about 240X speed-up for the 256x256 pixel matrix.

Effect of High Injection Pressure on Mixture Formation, Burning Process and Combustion Characteristics in Diesel Combustion

The mixture formation prior to the ignition process plays as a key element in the diesel combustion. Parametric studies of mixture formation and ignition process in various injection parameter has received considerable attention in potential for reducing emissions. Purpose of this study is to clarify the effects of injection pressure on mixture formation and ignition especially during ignition delay period, which have to be significantly influences throughout the combustion process and exhaust emissions. This study investigated the effects of injection pressure on diesel combustion fundamentally using rapid compression machine. The detail behavior of mixture formation during ignition delay period was investigated using the schlieren photography system with a high speed camera. This method can capture spray evaporation, spray interference, mixture formation and flame development clearly with real images. Ignition process and flame development were investigated by direct photography method using a light sensitive high-speed color digital video camera. The injection pressure and air motion are important variable that strongly affect to the fuel evaporation, endothermic and prolysis process during ignition delay. An increased injection pressure makes spray tip penetration longer and promotes a greater amount of fuel-air mixing occurs during ignition delay. A greater quantity of fuel prepared during ignition delay period thus predominantly promotes more rapid heat release.

Porous Particles Drying in a Vertical Upward Pneumatic Conveying Dryer

A steady two-phase flow model has been developed to simulate the drying process of porous particle in a pneumatic conveying dryer. The model takes into account the momentum, heat and mass transfer between the continuous phase and the dispersed phase. A single particle model was employed to calculate the evaporation rate. In this model the pore structure is simplified to allow the dominant evaporation mechanism to be readily identified at all points within the duct. The predominant mechanism at any time depends upon the pressure, temperature and the diameter of pore from which evaporating is occurring. The model was validated against experimental studies of pneumatic transport at low and high speeds as well as pneumatic drying. The effects of operating conditions on the dryer parameters are studied numerically. The present results show that the drying rate is enhanced as the inlet gas temperature and the gas flow rate increase and as the solid mass flow rate deceases. The present results also demonstrate the necessity of measuring the inlet gas velocity or the solid concentration in any experimental analysis.

Seamless Flow of Voluminous Data in High Speed Network without Congestion Using Feedback Mechanism

Continuously growing needs for Internet applications that transmit massive amount of data have led to the emergence of high speed network. Data transfer must take place without any congestion and hence feedback parameters must be transferred from the receiver end to the sender end so as to restrict the sending rate in order to avoid congestion. Even though TCP tries to avoid congestion by restricting the sending rate and window size, it never announces the sender about the capacity of the data to be sent and also it reduces the window size by half at the time of congestion therefore resulting in the decrease of throughput, low utilization of the bandwidth and maximum delay. In this paper, XCP protocol is used and feedback parameters are calculated based on arrival rate, service rate, traffic rate and queue size and hence the receiver informs the sender about the throughput, capacity of the data to be sent and window size adjustment, resulting in no drastic decrease in window size, better increase in sending rate because of which there is a continuous flow of data without congestion. Therefore as a result of this, there is a maximum increase in throughput, high utilization of the bandwidth and minimum delay. The result of the proposed work is presented as a graph based on throughput, delay and window size. Thus in this paper, XCP protocol is well illustrated and the various parameters are thoroughly analyzed and adequately presented.

Design of the Roller Clamp Robotic Assembly System

This work deals with the design of the robotic assembly system for the roller clamps. The task is characterized by high speed, high yield and safety engagement. This paper describes the design of different parts of an automated high speed machine to assemble the parts of roller clamps. The roller clamp robotic assembly system performs various processes in the assembly line which include clamp body and roller feeding, inserting the roller into the clamp body, and dividing the rejected clamp and successfully assembled clamp into their own tray. The electrical/electronics design of the machine is discussed. The target is to design a cost effective, minimum maintenance and high speed machine for the industry applications.

A 10 Giga VPN Accelerator Board for Trust Channel Security System

This paper proposes a VPN Accelerator Board (VPN-AB), a virtual private network (VPN) protocol designed for trust channel security system (TCSS). TCSS supports safety communication channel between security nodes in internet. It furnishes authentication, confidentiality, integrity, and access control to security node to transmit data packets with IPsec protocol. TCSS consists of internet key exchange block, security association block, and IPsec engine block. The internet key exchange block negotiates crypto algorithm and key used in IPsec engine block. Security Association blocks setting-up and manages security association information. IPsec engine block treats IPsec packets and consists of networking functions for communication. The IPsec engine block should be embodied by H/W and in-line mode transaction for high speed IPsec processing. Our VPN-AB is implemented with high speed security processor that supports many cryptographic algorithms and in-line mode. We evaluate a small TCSS communication environment, and measure a performance of VPN-AB in the environment. The experiment results show that VPN-AB gets a performance throughput of maximum 15.645Gbps when we set the IPsec protocol with 3DES-HMAC-MD5 tunnel mode.

Implementation of Adder-Subtracter Design with VerilogHDL

According to the density of the chips, designers are trying to put so any facilities of computational and storage on single chips. Along with the complexity of computational and storage circuits, the designing, testing and debugging become more and more complex and expensive. So, hardware design will be built by using very high speed hardware description language, which is more efficient and cost effective. This paper will focus on the implementation of 32-bit ALU design based on Verilog hardware description language. Adder and subtracter operate correctly on both unsigned and positive numbers. In ALU, addition takes most of the time if it uses the ripple-carry adder. The general strategy for designing fast adders is to reduce the time required to form carry signals. Adders that use this principle are called carry look- ahead adder. The carry look-ahead adder is to be designed with combination of 4-bit adders. The syntax of Verilog HDL is similar to the C programming language. This paper proposes a unified approach to ALU design in which both simulation and formal verification can co-exist.

Multicast Optimization Techniques using Best Effort Genetic Algorithms

Multicast Network Technology has pervaded our lives-a few examples of the Networking Techniques and also for the improvement of various routing devices we use. As we know the Multicast Data is a technology offers many applications to the user such as high speed voice, high speed data services, which is presently dominated by the Normal networking and the cable system and digital subscriber line (DSL) technologies. Advantages of Multi cast Broadcast such as over other routing techniques. Usually QoS (Quality of Service) Guarantees are required in most of Multicast applications. The bandwidth-delay constrained optimization and we use a multi objective model and routing approach based on genetic algorithm that optimizes multiple QoS parameters simultaneously. The proposed approach is non-dominated routes and the performance with high efficiency of GA. Its betterment and high optimization has been verified. We have also introduced and correlate the result of multicast GA with the Broadband wireless to minimize the delay in the path.