Abstract: An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.
Abstract: In this paper by measuring the cutting forces the effect
of the tool shape and qualifications (sharp and worn cutting tools of
both vee and knife edge profile) and cutting conditions (depth of cut
and cutting speed) in the turning operation on the tool deflection and
cutting force is investigated. The workpiece material was mild steel
and the cutting tool was made of high speed steel. Cutting forces
were measured by a dynamometer (type P.E.I. serial No 154). The
dynamometer essentially consisted of a cantilever structure which
held the cutting tool. Deflection of the cantilever was measured by an
L.V.D.T (Mercer 122) deflection indicator. No cutting fluid was used
during the turning operations. A modern CNC lathe machine (Okuma
LH35-N) was used for the tests. It was noted that worn vee profile
tools tended to produce a greater increase in the vertical force
component than the axial component, whereas knife tools tended to
show a more pronounced increase in the axial component.
Abstract: In this article, a method has been offered to classify
normal and defective tiles using wavelet transform and artificial
neural networks. The proposed algorithm calculates max and min
medians as well as the standard deviation and average of detail
images obtained from wavelet filters, then comes by feature vectors
and attempts to classify the given tile using a Perceptron neural
network with a single hidden layer. In this study along with the
proposal of using median of optimum points as the basic feature and
its comparison with the rest of the statistical features in the wavelet
field, the relational advantages of Haar wavelet is investigated. This
method has been experimented on a number of various tile designs
and in average, it has been valid for over 90% of the cases. Amongst
the other advantages, high speed and low calculating load are
prominent.
Abstract: In this study, we experiment on precise control outlet
temperature of water from the water cooler with hot-gas bypass
method based on PI control logic for machine tool. Recently, technical
trend for machine tools is focused on enhancement of speed and
accuracy. High speedy processing causes thermal and structural
deformation of objects from the machine tools. Water cooler has to be
applied to machine tools to reduce the thermal negative influence with
accurate temperature controlling system. The goal of this study is to
minimize temperature error in steady state. In addition, control period
of an electronic expansion valve were considered to increment of
lifetime of the machine tools and quality of product with a water
cooler.
Abstract: Fast delay estimation methods, as opposed to
simulation techniques, are needed for incremental performance
driven layout synthesis. On-chip inductive effects are becoming
predominant in deep submicron interconnects due to increasing clock
speed and circuit complexity. Inductance causes noise in signal
waveforms, which can adversely affect the performance of the circuit
and signal integrity. Several approaches have been put forward which
consider the inductance for on-chip interconnect modelling. But for
even much higher frequency, of the order of few GHz, the shunt
dielectric lossy component has become comparable to that of other
electrical parameters for high speed VLSI design. In order to cope up
with this effect, on-chip interconnect has to be modelled as
distributed RLCG line. Elmore delay based methods, although
efficient, cannot accurately estimate the delay for RLCG interconnect
line. In this paper, an accurate analytical delay model has been
derived, based on first and second moments of RLCG
interconnection lines. The proposed model considers both the effect
of inductance and conductance matrices. We have performed the
simulation in 0.18μm technology node and an error of as low as less
as 5% has been achieved with the proposed model when compared to
SPICE. The importance of the conductance matrices in interconnect
modelling has also been discussed and it is shown that if G is
neglected for interconnect line modelling, then it will result an delay
error of as high as 6% when compared to SPICE.