Low Jitter ADPLL based Clock Generator for High Speed SoC Applications
An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.
[1] R.E. Best, "Phase-Locked Loops Principle, Design and Applications".
New York; McGraw-Hill, Feb 2000.
[2] T. Hsu, B. Shieh and C. Lee, "An all-digital phase-locked loop (ADPLL)-
based clock recovery circuit," IEEE Journal of Solid-State Circuits, vol. 34,
pp.1063-1073, Aug 1999.
[3] Ching-Che Chung, Duo Sheng and Chen-Yi Lee, "An All-Digital Phase-
Locked Loop with High-Resolution for SoC Applications", VLSI Design
Automation and Test, 2006 International Symposium, pg. 1 - 4, April 2006.
[4] E. Mokhtari and M.Sawan,"CMOS High Resolution All-Digital Phase
Locked Loop", 46th IEEE International symposium on Circuits and systems,
pg 221-224, Vol 1, 27-30 Dec, 2003.
[5] Read Stefo, Jorg Schreiter, Jens-Uwe SchliiOler and Rene SchiiRny,
"High Resolution ADPLL Frequency Synthesizer for FPGA- and ASIC-based
Applications", Proceedings. IEEE International Conference, pg 28 - 34, Dec
2003.
[6] Masami Kihara, Sadayasu Ono and Pekka Eskelinen, "Digital Clocks for
Synchronization and Communications", John Wiley & Sons, 2003.
[7] A. Telbal, J. M. Noras2, M. Abou El Elal, and B.AlMasharyl "Jitter
minimization in Digital Transmission using dual phase locked loops", 17th
International Conference on Microelectronics, pg 270 - 273, Dec 2005.
[8] B. Sai Pramod Reddy, N. Krishnaprasad, S. Moorthi, J. Raja paul
perinbam, "An All Digital Phase Locked Loop for Ultra fast locking",
Proceedings of National Conference on Emerging Trends in Engineering and
Technology, April 2008.
[1] R.E. Best, "Phase-Locked Loops Principle, Design and Applications".
New York; McGraw-Hill, Feb 2000.
[2] T. Hsu, B. Shieh and C. Lee, "An all-digital phase-locked loop (ADPLL)-
based clock recovery circuit," IEEE Journal of Solid-State Circuits, vol. 34,
pp.1063-1073, Aug 1999.
[3] Ching-Che Chung, Duo Sheng and Chen-Yi Lee, "An All-Digital Phase-
Locked Loop with High-Resolution for SoC Applications", VLSI Design
Automation and Test, 2006 International Symposium, pg. 1 - 4, April 2006.
[4] E. Mokhtari and M.Sawan,"CMOS High Resolution All-Digital Phase
Locked Loop", 46th IEEE International symposium on Circuits and systems,
pg 221-224, Vol 1, 27-30 Dec, 2003.
[5] Read Stefo, Jorg Schreiter, Jens-Uwe SchliiOler and Rene SchiiRny,
"High Resolution ADPLL Frequency Synthesizer for FPGA- and ASIC-based
Applications", Proceedings. IEEE International Conference, pg 28 - 34, Dec
2003.
[6] Masami Kihara, Sadayasu Ono and Pekka Eskelinen, "Digital Clocks for
Synchronization and Communications", John Wiley & Sons, 2003.
[7] A. Telbal, J. M. Noras2, M. Abou El Elal, and B.AlMasharyl "Jitter
minimization in Digital Transmission using dual phase locked loops", 17th
International Conference on Microelectronics, pg 270 - 273, Dec 2005.
[8] B. Sai Pramod Reddy, N. Krishnaprasad, S. Moorthi, J. Raja paul
perinbam, "An All Digital Phase Locked Loop for Ultra fast locking",
Proceedings of National Conference on Emerging Trends in Engineering and
Technology, April 2008.
@article{"International Journal of Electrical, Electronic and Communication Sciences:49919", author = "Moorthi S. and Meganathan D. and Janarthanan D. and Praveen Kumar P. and J. Raja paul perinbam", title = "Low Jitter ADPLL based Clock Generator for High Speed SoC Applications", abstract = "An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.", keywords = "All Digital Phase Locked Loop (ADPLL), Systemon-Chip (SoC), Phase Locked Loop (PLL), Very High speedIntegrated Circuit (VHSIC) Hardware Description Language(VHDL), Digitally Controlled Oscillator (DCO), Phase frequencydetector (PFD) and Voltage Controlled Oscillator (VCO).", volume = "2", number = "6", pages = "1061-5", }