Abstract: In this paper, an ultra low power and low jitter 12bit
CMOS digitally controlled oscillator (DCO) design is presented.
Based on a ring oscillator implemented with low power Schmitt
trigger based inverters. Simulation of the proposed DCO using 32nm
CMOS Predictive Transistor Model (PTM) achieves controllable
frequency range of 550MHz~830MHz with a wide linearity and high
resolution. Monte Carlo simulation demonstrates that the time-period
jitter due to random power supply fluctuation is under 31ps and the
power consumption is 0.5677mW at 750MHz with 1.2V power
supply and 0.53-ps resolution. The proposed DCO has a good
robustness to voltage and temperature variations and better linearity
comparing to the conventional design.
Abstract: An efficient architecture for low jitter All Digital
Phase Locked Loop (ADPLL) suitable for high speed SoC
applications is presented in this paper. The ADPLL is designed using
standard cells and described by Hardware Description Language
(HDL). The ADPLL implemented in a 90 nm CMOS process can
operate from 10 to 200 MHz and achieve worst case frequency
acquisition in 14 reference clock cycles. The simulation result shows
that PLL has cycle to cycle jitter of 164 ps and period jitter of 100 ps
at 100MHz. Since the digitally controlled oscillator (DCO) can
achieve both high resolution and wide frequency range, it can meet
the demands of system-level integration. The proposed ADPLL can
easily be ported to different processes in a short time. Thus, it can
reduce the design time and design complexity of the ADPLL, making
it very suitable for System-on-Chip (SoC) applications.