High Speed and Ultra Low-voltage CMOS NAND and NOR Domino Gates

In this paper we ultra low-voltage and high speed CMOS domino logic. For supply voltages below 500mV the delay for a ultra low-voltage NAND2 gate is aproximately 10% of a complementary CMOS inverter. Furthermore, the delay variations due to mismatch is much less than for conventional CMOS. Differential domino gates for AND/NAND and OR/NOR operation are presented.

• Yngvar Berg
• Omid Mirmotahari

• Low-voltage
• high-speed
• NAND
• NOR
• CMOS.

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