Abstract: In the hardening energy context, the transport sector
which constitutes a large worldwide energy demand has to be
improving for decrease energy demand and global warming impacts.
In a controversial situation where subsists an increasing demand for
long-distance and high-speed travels, high-speed trains offer many
advantages, as consuming significantly less energy than road or air
transports.
At the project phase of new rail infrastructures, it is nowadays
important to characterize accurately the energy that will be induced
by its operation phase, in addition to other more classical criteria as
construction costs and travel time.
Current literature consumption models used to estimate railways
operation phase are obsolete or not enough accurate for taking into
account the newest train or railways technologies.
In this paper, an updated model of consumption for high-speed is
proposed, based on experimental data obtained from full-scale tests
performed on a new high-speed line. The assessment of the model
is achieved by identifying train parameters and measured power
consumptions for more than one hundred train routes. Perspectives
are then discussed to use this updated model for accurately assess
the energy impact of future railway infrastructures.
Abstract: Bubble generation was observed using a high-speed
camera in subcooled flow boiling at low void fraction. Constant heat
flux was applied on one side of an upward rectangular channel to
make heated test channel. Water as a working fluid from high
subcooling to near saturation temperature was injected step by step to
investigate bubble behavior during void development. Experiments
were performed in two different pressures condition close to 2bar and
4bar. It was observed that in high subcooling when boiling was
commenced, bubble after nucleation departed its origin and slid
beside heated surface. In an observation window mean release
frequency of bubble fb,mean, nucleation site Ns and mean bubble
volume Vb,mean in each step of experiments were measured to
investigate wall vaporization rate. It was found that in proximity of
PNVG vaporization rate was increased significantly in compare with
condensation rate which remained in low value.
Abstract: Since 2004, we have been developing an in-situ storage image sensor (ISIS) that captures more than 100 consecutive images at a frame rate of 10 Mfps with ultra-high sensitivity as well as the video camera for use with this ISIS. Currently, basic research is continuing in an attempt to increase the frame rate up to 100 Mfps and above. In order to suppress electro-magnetic noise at such high frequency, a digital-noiseless imaging transfer scheme has been developed utilizing solely sinusoidal driving voltages. This paper presents highly efficient-yet-accurate expressions to estimate attenuation as well as phase delay of driving voltages through RC networks of an ultra-high-speed image sensor. Elmore metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE data, we found a simple expression that significantly improves the accuracy of the approximation. Similarly, another simple closed-form model to estimate phase delay through fundamental RC networks is also obtained. Estimation error of both expressions is much less than previous works, only less 2% for most of the cases . The framework of this analysis can be extended to address similar issues of other VLSI structures.
Abstract: I/O workload is a critical and important factor to
analyze I/O pattern and to maximize file system performance.
However to measure I/O workload on running distributed parallel file
system is non-trivial due to collection overhead and large volume of
data. In this paper, we measured and analyzed file system activities on
two large-scale cluster systems which had TFlops level high
performance computation resources. By comparing file system
activities of 2009 with those of 2006, we analyzed the change of I/O
workloads by the development of system performance and high-speed
network technology.
Abstract: This paper describes the pipeline architecture of
high-speed modified Booth multipliers. The proposed multiplier
circuits are based on the modified Booth algorithm and the pipeline
technique which are the most widely used to accelerate the
multiplication speed. In order to implement the optimally pipelined
multipliers, many kinds of experiments have been conducted. The
speed of the multipliers is greatly improved by properly deciding the
number of pipeline stages and the positions for the pipeline registers to
be inserted. We described the proposed modified Booth multiplier
circuits in Verilog HDL and synthesized the gate-level circuits using
0.13um standard cell library. The resultant multiplier circuits show
better performance than others. Since the proposed multipliers operate
at GHz ranges, they can be used in the systems requiring very high
performance.
Abstract: In this paper we present an energy efficient match-line
(ML) sensing scheme for high-speed ternary content-addressable
memory (TCAM). The proposed scheme isolates the sensing unit of
the sense amplifier from the large and variable ML capacitance. It
employs feedback in the sense amplifier to successfully detect a
match while keeping the ML voltage swing low. This reduced voltage
swing results in large energy saving. Simulation performed using
130nm 1.2V CMOS logic shows at least 30% total energy saving in
our scheme compared to popular current race (CR) scheme for
similar search speed. In terms of speed, dynamic energy, peak power
consumption and transistor count our scheme also shows better
performance than mismatch-dependant (MD) power allocation
technique which also employs feedback in the sense amplifier.
Additionally, the implementation of our scheme is simpler than CR
or MD scheme because of absence of analog control voltage and
programmable delay circuit as have been used in those schemes.
Abstract: In this paper, we propose a new architecture for the implementation of the N-point Fast Fourier Transform (FFT), based on the Radix-2 Decimation in Frequency algorithm. This architecture is based on a pipeline circuit that can process a stream of samples and produce two FFT transform samples every clock cycle. Compared to existing implementations the architecture proposed achieves double processing speed using the same circuit complexity.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: The machining performance is determined by the
frequency characteristics of the machine-tool structure and the
dynamics of the cutting process. Therefore, the prediction of dynamic
vibration behavior of spindle tool system is of great importance for the
design of a machine tool capable of high-precision and high-speed
machining. The aim of this study is to develop a finite element model
to predict the dynamic characteristics of milling machine tool and
hence evaluate the influence of the preload of the spindle bearings. To
this purpose, a three dimensional spindle bearing model of a high
speed engraving spindle tool was created. In this model, the rolling
interfaces with contact stiffness defined by Harris model were used to
simulate the spindle bearing components. Then a full finite element
model of a vertical milling machine was established by coupling the
spindle tool unit with the machine frame structure. Using this model,
the vibration mode that had a dominant influence on the dynamic
stiffness was determined. The results of the finite element simulations
reveal that spindle bearing with different preloads greatly affect the
dynamic behavior of the spindle tool unit and hence the dynamic
responses of the vertical column milling system. These results were
validated by performing vibration on the individual spindle tool unit
and the milling machine prototype, respectively. We conclude that
preload of the spindle bearings is an important component affecting
the dynamic characteristics and machining performance of the entire
vertical column structure of the milling machine.
Abstract: We present an explicit expression to estimate driving voltage attenuation through RC networks representation of an ultrahigh- speed image sensor. Elmore delay metric for a fundamental RC chain is employed as the first-order approximation. By application of dimensional analysis to SPICE simulation data, we found a simple expression that significantly improves the accuracy of the approximation. Estimation error of the resultant expression for uniform RC networks is less than 2%. Similarly, another simple closed-form model to estimate 50 % delay through fundamental RC networks is also derived with sufficient accuracy. The framework of this analysis can be extended to address delay or attenuation issues of other VLSI structures.
Abstract: A 3.5-bit stage of the CMOS pipelined ADC is proposed. In this report, the main part of 3.5-bit stage ADC is introduced. How the MDAC, comparator and encoder worked and designed are shown in details. Besides, an OTA which is used in fully differential pipelined ADC was described. Using gain-boost architecture with differential amplifier, this OTA achieve high-gain and high-speed. This design was using CMOS 0.18um process and simulation in Cadence. The result of the simulation shows that the OTA has a gain up to 80dB, the unity gain bandwidth of about 1.138GHz with 2pF load.
Abstract: In this paper the authors propose a protocol, which uses Elliptic Curve Cryptography (ECC) based on the ElGamal-s algorithm, for sending small amounts of data via an authentication server. The innovation of this approach is that there is no need for a symmetric algorithm or a safe communication channel such as SSL. The reason that ECC has been chosen instead of RSA is that it provides a methodology for obtaining high-speed implementations of authentication protocols and encrypted mail techniques while using fewer bits for the keys. This means that ECC systems require smaller chip size and less power consumption. The proposed protocol has been implemented in Java to analyse its features and vulnerabilities in the real world.
Abstract: The aerodynamic noise radiation from a side view mirror (SVM) in the high-speed airflow is calculated by the combination of unsteady incompressible fluid flow analysis and acoustic analysis. The transient flow past the generic SVM is simulated with variable turbulence model, namely DES Detached Eddy Simulation and LES (Large Eddy Simulation). Detailed velocity vectors and contour plots of the time-varying velocity and pressure fields are presented along cut planes in the flow-field. Mean and transient pressure are also monitored at several points in the flow field and compared to corresponding experimentally data published in literature. The acoustic predictions made using the Ffowcs-Williams-Hawkins acoustic analogy (FW-H) and the boundary element (BEM).
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: High-frequency (HF) communications have been used by military organizations for more than 90 years. The opportunity of very long range communications without the need for advanced equipment makes HF a convenient and inexpensive alternative of satellite communications. Besides the advantages, voice and data transmission over HF is a challenging task, because the HF channel generally suffers from Doppler shift and spread, multi-path, cochannel interference, and many other sources of noise. In constructing an HF data modem, all these effects must be taken into account. STANAG 4539 is a NATO standard for high-speed data transmission over HF. It allows data rates up to 12800 bps over an HF channel of 3 kHz. In this work, an efficient implementation of STANAG 4539 on a single Texas Instruments- TMS320C6747 DSP chip is described. The state-of-the-art algorithms used in the receiver and the efficiency of the implementation enables real-time high-speed data / digitized voice transmission over poor HF channels.
Abstract: The fine structure of supercavitation in the wake of a
symmetrical cylinder is studied with high-speed video cameras. The
flow is observed in a cavitation tunnel at the speed of 8m/sec when the
sidewall and the wake are partially filled with the massive cavitation
bubbles. The present experiment observed that a two-dimensional
ripple wave with a wave length of 0.3mm is propagated in a
downstream direction, and then abruptly increases to a thicker
three-dimensional layer. IR-photography recorded that the wakes
originated from the horseshoe vortexes alongside the cylinder. The
wake was developed to inside the dead water zone, which absorbed the
bubbly wake propelled from the separated vortices at the center of the
cylinder. A remote sensing classification technique (maximum most
likelihood) determined that the surface porosity was 0.2, and the mean
speed in the mixed wake was 7m/sec. To confirm the existence of
two-dimensional wave motions in the interface, the experiments were
conducted at a very low frequency, and showed similar gravity waves
in both the upper and lower interfaces.
Abstract: This paper presents a real-time defect detection
algorithm for high-speed steel bar in coil. Because the target speed is
very high, proposed algorithm should process quickly the large
volumes of image for real-time processing. Therefore, defect detection
algorithm should satisfy two conflicting requirements of reducing the
processing time and improving the efficiency of defect detection. To
enhance performance of detection, edge preserving method is
suggested for noise reduction of target image. Finally, experiment
results show that the proposed algorithm guarantees the condition of
the real-time processing and accuracy of detection.
Abstract: The three-time-scale plant model of a wind power
generator, including a wind turbine, a flexible vertical shaft, a Variable
Inertia Flywheel (VIF) module, an Active Magnetic Bearing (AMB)
unit and the applied wind sequence, is constructed. In order to make
the wind power generator be still able to operate as the spindle speed
exceeds its rated speed, the VIF is equipped so that the spindle speed
can be appropriately slowed down once any stronger wind field is
exerted. To prevent any potential damage due to collision by shaft
against conventional bearings, the AMB unit is proposed to regulate
the shaft position deviation. By singular perturbation order-reduction
technique, a lower-order plant model can be established for the
synthesis of feedback controller. Two major system parameter
uncertainties, an additive uncertainty and a multiplicative uncertainty,
are constituted by the wind turbine and the VIF respectively.
Frequency Shaping Sliding Mode Control (FSSMC) loop is proposed
to account for these uncertainties and suppress the unmodeled
higher-order plant dynamics. At last, the efficacy of the FSSMC is
verified by intensive computer and experimental simulations for
regulation on position deviation of the shaft and counter-balance of
unpredictable wind disturbance.
Abstract: The objective of this research was to study factors,
which were affected on surface roughness in high speed milling of
hardened tool steel. Material used in the experiment was tool steel JIS
SKD 61 that hardened on 60 ±2 HRC. Full factorial experimental
design was conducted on 3 factors and 3 levels (3
3
designs) with 2
replications. Factors were consisted of cutting speed, feed rate, and
depth of cut. The results showed that influenced factor affected to
surface roughness was cutting speed, feed rate and depth of cut which
showed statistical significant. Higher cutting speed would cause on
better surface quality. On the other hand, higher feed rate would cause
on poorer surface quality. Interaction of factor was found that cutting
speed and depth of cut were significantly to surface quality. The
interaction of high cutting speed associated with low depth of cut
affected to better surface quality than low cutting speed and high depth
of cut.
Abstract: Grid computing is a group of clusters connected over
high-speed networks that involves coordinating and sharing
computational power, data storage and network resources operating
across dynamic and geographically dispersed locations. Resource
management and job scheduling are critical tasks in grid computing.
Resource selection becomes challenging due to heterogeneity and
dynamic availability of resources. Job scheduling is a NP-complete
problem and different heuristics may be used to reach an optimal or
near optimal solution. This paper proposes a model for resource and
job scheduling in dynamic grid environment. The main focus is to
maximize the resource utilization and minimize processing time of
jobs. Grid resource selection strategy is based on Max Heap Tree
(MHT) that best suits for large scale application and root node of
MHT is selected for job submission. Job grouping concept is used to
maximize resource utilization for scheduling of jobs in grid
computing. Proposed resource selection model and job grouping
concept are used to enhance scalability, robustness, efficiency and
load balancing ability of the grid.