Abstract: The high prevalence of cardiovascular diseases has provoked a raising interest in the development of mathematical models in order to evaluate the cardiovascular function both under physiological and pathological conditions. In this paper, a physical model of the cardiovascular system with intrinsic regulation is presented and implemented by using the object-oriented Modelica simulation software tools. For this task, a multi-compartmental system previously validated with physiological data has been built, based on the interconnection of cardiovascular elements such as resistances, capacitances and pumping among others, by following an electrohydraulic analogy. The results obtained under both physiological and pathological scenarios provide an easy interpretative key to analyze the hemodynamic behavior of the patient. The described approach represents a valuable tool in the teaching of physiology for graduate medical and nursing students among others.
Abstract: This paper discusses the undesirable charge transfer
through the parasitic capacitances of the input transistors in a
multi-inputs voltage sense amplifier. Its intrinsic rail-to-rail voltage
transitions at the output nodes inevitably disturb the input sides
through the capacitive coupling between the outputs and inputs. Then,
it can possible degrade the stabilities of the reference voltage levels.
Moreover, it becomes more serious in multi-channel systems by
altering them for other channels, and so degrades the linearity of the
overall systems. In order to alleviate the internal node voltage
transition, the internal node stabilization techniques are proposed. It
achieves 45% and 40% improvements for node stabilization and input
referred disturbance, respectively.
Abstract: This paper discusses the undesirable charge transfer by the parasitic capacitances of the input transistors in a voltage sense amplifier. Due to its intrinsic rail-to-rail voltage transition, the input sides are inevitably disturbed. It can possible disturb the stabilities of the reference voltage levels. Moreover, it becomes serious in multi-channel systems by altering them for other channels, and so degrades the linearity of the systems. In order to alleviate the internal node voltage transition, the internal node stabilization technique is proposed by utilizing an additional biasing circuit. It achieves 47% and 43% improvements for node stabilization and input referred disturbance, respectively.
Abstract: The present paper describes the development of a low cost, highly accurate low capacitance measurement system that can be used over a range of 0 – 400 pF with a resolution of 1 pF. The range of capacitance may be easily altered by a simple resistance or capacitance variation of the measurement circuit. This capacitance measurement system uses quad two-input NAND Schmitt trigger circuit CD4093B with hysteresis for the measurement and this system is integrated with PIC 18F2550 microcontroller for data acquisition purpose. The microcontroller interacts with software developed in the PC end through USB architecture and an attractive graphical user interface (GUI) based system is developed in the PC end to provide the user with real time, online display of capacitance under measurement. The system uses a differential mode of capacitance measurement, with reference to a trimmer capacitance, that effectively compensates lead capacitances, a notorious error encountered in usual low capacitance measurements. The hysteresis provided in the Schmitt-trigger circuits enable reliable operation of the system by greatly minimizing the possibility of false triggering because of stray interferences, usually regarded as another source of significant error. The real life testing of the proposed system showed that our measurements could produce highly accurate capacitance measurements, when compared to cutting edge, high end digital capacitance meters.
Abstract: In this paper, a power laterally-diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET) on In0.53Ga0.47As is presented. The device utilizes a thicker field-oxide with low dielectric constant under the field-plate in order to achieve possible reduction in device capacitances and reduced-surface-field effect. Using 2D numerical simulations, performance of the proposed device is analyzed and compared with that of the conventional LDMOSFET. The proposed structure provides 50% increase in the breakdown voltage, 21% increase in transit frequency, and 72% improvement in figure-of-merit over the conventional device for same cell pitch.
Abstract: Force sensor has been used as requisite for knowing information on the amount and the directions of forces on the skin surface. We have developed a four-degrees-of-freedom capacitive force sensor (approximately 20×20×5 mm3) that has a flexible structure and sixteen parallel plate capacitors. An iterative algorithm was developed for estimating four displacements from the sixteen capacitances using fourth-order polynomial approximation of characteristics between capacitance and displacement. The estimation results from measured capacitances had large error caused by deterioration of the characteristics. In this study, effective capacitors had major information were selected on the basis of the capacitance change range and the characteristic shape. Maximum errors in calibration and non-calibration points were 25%and 6.8%.However the maximum error was larger than desired value, the smallness of averaged value indicated the occurrence of a few large error points. On the other hand, error in non-calibration point was within desired value.
Abstract: An on chip low drop out voltage regulator that
employs elegant compensation scheme is presented in this paper. The
novelty in this design is that the device parasitic capacitances are
exploited for compensation at different loads. The proposed LDO is
designed to provide a constant voltage of 1.2V and is implemented in
UMC 180 nano meter CMOS technology. The voltage regulator
presented improves stability even at lighter loads and enhances line
and load regulation.
Abstract: This paper proposes a low power SRAM based on
five transistor SRAM cell. Proposed SRAM uses novel word-line
decoding such that, during read/write operation, only selected cell
connected to bit-line whereas, in conventional SRAM (CV-SRAM),
all cells in selected row connected to their bit-lines, which in turn
develops differential voltages across all bit-lines, and this makes
energy consumption on unselected bit-lines. In proposed SRAM
memory array divided into two halves and this causes data-line
capacitance to reduce. Also proposed SRAM uses one bit-line and
thus has lower bit-line leakage compared to CV-SRAM.
Furthermore, the proposed SRAM incurs no area overhead, and has
comparable read/write performance versus the CV-SRAM.
Simulation results in standard 0.25μm CMOS technology shows in
worst case proposed SRAM has 80% smaller dynamic energy
consumption in each cycle compared to CV-SRAM. Besides, energy
consumption in each cycle of proposed SRAM and CV-SRAM
investigated analytically, the results of which are in good agreement
with the simulation results.
Abstract: Average current analysis checking the impact of
current flow is very important to guarantee the reliability of
semiconductor systems. As semiconductor process technologies
improve, the coupling capacitance often become bigger than self
capacitances. In this paper, we propose an analytic technique for
analyzing average current on interconnects in multi-conductor
structures. The proposed technique has shown to yield the acceptable
errors compared to HSPICE results while providing computational
efficiency.
Abstract: A high-frequency low-power sinusoidal quadrature
oscillator is presented through the use of two 2nd-order low-pass
current-mirror (CM)-based filters, a 1st-order CM low-pass filter and
a CM bilinear transfer function. The technique is relatively simple
based on (i) inherent time constants of current mirrors, i.e. the
internal capacitances and the transconductance of a diode-connected
NMOS, (ii) a simple negative resistance RN formed by a resistor load
RL of a current mirror. Neither external capacitances nor inductances
are required. As a particular example, a 1.9-GHz, 0.45-mW, 2-V
CMOS low-pass-filter-based all-current-mirror sinusoidal quadrature
oscillator is demonstrated. The oscillation frequency (f0) is 1.9 GHz
and is current-tunable over a range of 370 MHz or 21.6 %. The
power consumption is at approximately 0.45 mW. The amplitude
matching and the quadrature phase matching are better than 0.05 dB
and 0.15°, respectively. Total harmonic distortions (THD) are less
than 0.3 %. At 2 MHz offset from the 1.9 GHz, the carrier to noise
ratio (CNR) is 90.01 dBc/Hz whilst the figure of merit called a
normalized carrier-to-noise ratio (CNRnorm) is 153.03 dBc/Hz. The
ratio of the oscillation frequency (f0) to the unity-gain frequency (fT)
of a transistor is 0.25. Comparisons to other approaches are also
included.
Abstract: A new digital transceiver circuit for asynchronous frame detection is proposed where both the transmitter and receiver contain all digital components, thereby avoiding possible use of conventional devices like monostable multivibrators with unstable external components such as resistances and capacitances. The proposed receiver circuit, in particular, uses a combinational logic block yielding an output which changes its state as soon as the start bit of a new frame is detected. This, in turn, helps in generating an efficient receiver sampling clock. A data latching circuit is also used in the receiver to latch the recovered data bits in any new frame. The proposed receiver structure is also extended from 4- bit information to any general n data bits within a frame with a common expression for the output of the combinational logic block. Performance of the proposed hardware design is evaluated in terms of time delay, reliability and robustness in comparison with the standard schemes using monostable multivibrators. It is observed from hardware implementation that the proposed circuit achieves almost 33 percent speed up over any conventional circuit.