A Low Power SRAM Base on Novel Word-Line Decoding

This paper proposes a low power SRAM based on five transistor SRAM cell. Proposed SRAM uses novel word-line decoding such that, during read/write operation, only selected cell connected to bit-line whereas, in conventional SRAM (CV-SRAM), all cells in selected row connected to their bit-lines, which in turn develops differential voltages across all bit-lines, and this makes energy consumption on unselected bit-lines. In proposed SRAM memory array divided into two halves and this causes data-line capacitance to reduce. Also proposed SRAM uses one bit-line and thus has lower bit-line leakage compared to CV-SRAM. Furthermore, the proposed SRAM incurs no area overhead, and has comparable read/write performance versus the CV-SRAM. Simulation results in standard 0.25μm CMOS technology shows in worst case proposed SRAM has 80% smaller dynamic energy consumption in each cycle compared to CV-SRAM. Besides, energy consumption in each cycle of proposed SRAM and CV-SRAM investigated analytically, the results of which are in good agreement with the simulation results.

Authors:

• Arash Azizi Mazreah
• Mohammad T. Manzuri Shalmani
• Hamid Barati
• Ali Barati
• Ali Sarchami

Keywords:

• SRAM
• write Operation
• read Operation
• capacitances
• dynamic energy consumption.

References:

[1] B. Amelifard, F. Fallah, and M. Pedram, "Low-leakage SRAM design
with dual Vt transistors", in Proc. Of 7th Int'l Symp. on Quality of
Electronic Designs, 2006.
[2] K. Martin, Digital Integrated Circuit Design, Oxford university press,
2000, pp.443-446.
[3] T. Hirose, H. Kuriyama, S. Mnmkami, K. Yuzuriha, T. Mukai, et al., "A
20-ns 4-Mb CMOS SRAM with Hierarchical Word Decoding
Architecture", IEEE J. of Solid-State Circuits, vol. 25, No.5, 1990, pp.
1068-1074.
[4] I. Carlson, S. Andersson, S. Natarajan, and A. Alvandpour, "A high
density, low leakage, 5T SRAM for embedded caches", in Proc. of
European Solid-State Circuits Conference, 2004, pp. 215-222.
[5] J. M. Rabaey, et al., Digital Integrated Circuits: A Design Perspective,
2nd ed., Prentice Hall, 2002, pp.209-211.