Abstract: Theory of Constraints has been emerging as an
important tool for optimization of manufacturing/service systems.
Goldratt in his first book “ The Goal " gave the introduction on
Theory of Constraints and its applications in a factory scenario. A
large number of production managers around the globe read this book
but only a few could implement it in their plants because the book did
not explain the steps to implement TOC in the factory. To overcome
these limitations, Goldratt wrote this book to explain TOC, DBR and
the method to implement it. In this paper, an attempt has been made
to summarize the salient features of TOC and DBR listed in the book
and the correct approach to implement TOC in a factory setting. The
simulator available along with the book was actually used by the
authors and the claim of Goldratt regarding the use of DBR and
Buffer management to ease the work of production managers was
tested and was found to be correct.
Abstract: The whole work is based on possibility to use Lego Mindstorms robotics systems to reduce costs. Lego Mindstorms consists of a wide variety of hardware components necessary to simulate, programme and test of robotics systems in practice. To programme algorithm, which simulates space using the ultrasonic sensor, was used development environment supplied with kit. Software Matlab was used to render values afterwards they were measured by ultrasonic sensor. The algorithm created for this paper uses theoretical knowledge from area of signal processing. Data being processed by algorithm are collected by ultrasonic sensor that scans 2D space in front of it. Ultrasonic sensor is placed on moving arm of robot which provides horizontal moving of sensor. Vertical movement of sensor is provided by wheel drive. The robot follows map in order to get correct positioning of measured data. Based on discovered facts it is possible to consider Lego Mindstorm for low-cost and capable kit for real-time modelling.
Abstract: Evolvable hardware (EHW) refers to a selfreconfiguration
hardware design, where the configuration is under
the control of an evolutionary algorithm (EA). A lot of research has
been done in this area several different EA have been introduced.
Every time a specific EA is chosen for solving a particular problem,
all its components, such as population size, initialization, selection
mechanism, mutation rate, and genetic operators, should be selected
in order to achieve the best results. In the last three decade a lot of
research has been carried out in order to identify the best parameters
for the EA-s components for different “test-problems". However
different researchers propose different solutions. In this paper the
behaviour of mutation rate on (1+λ) evolution strategy (ES) for
designing logic circuits, which has not been done before, has been
deeply analyzed. The mutation rate for an EHW system modifies
values of the logic cell inputs, the cell type (for example from AND
to NOR) and the circuit output. The behaviour of the mutation has
been analyzed based on the number of generations, genotype
redundancy and number of logic gates used for the evolved circuits.
The experimental results found provide the behaviour of the mutation
rate to be used during evolution for the design and optimization of
logic circuits. The researches on the best mutation rate during the last
40 years are also summarized.
Abstract: The following paper shows an interactive tool which
main purpose is to teach how to play a flute. It consists of three
stages the first one is the instruction and teaching process through a
software application, the second is the practice part when the user
starts to play the flute (hardware specially designed for this
application) this flute is capable of capturing how is being played the
flute and the final stage is the one in which the data captured are sent
to the software and the user is evaluated in order to give him / she a
correction or an acceptance
Abstract: This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.
Abstract: Block replacement algorithms to increase hit ratio
have been extensively used in cache memory management. Among
basic replacement schemes, LRU and FIFO have been shown to be
effective replacement algorithms in terms of hit rates. In this paper,
we introduce a flexible stack-based circuit which can be employed in
hardware implementation of both LRU and FIFO policies. We
propose a simple and efficient architecture such that stack-based
replacement algorithms can be implemented without the drawbacks
of the traditional architectures. The stack is modular and hence, a set
of stack rows can be cascaded depending on the number of blocks in
each cache set. Our circuit can be implemented in conjunction with
the cache controller and static/dynamic memories to form a cache
system. Experimental results exhibit that our proposed circuit
provides an average value of 26% improvement in storage bits and its
maximum operating frequency is increased by a factor of two
Abstract: In this work a new platform for mobile-health systems is
presented. System target application is providing decision support to
rescue corps or military medical personnel in combat areas. Software
architecture relies on a distributed client-server system that manages a
wireless ad-hoc networks hierarchy in which several different types of
client operate. Each client is characterized for different hardware and
software requirements. Lower hierarchy levels rely in a network of
completely custom devices that store clinical information and patient
status and are designed to form an ad-hoc network operating in the
2.4 GHz ISM band and complying with the IEEE 802.15.4 standard
(ZigBee). Medical personnel may interact with such devices, that are
called MICs (Medical Information Carriers), by means of a PDA
(Personal Digital Assistant) or a MDA (Medical Digital Assistant),
and transmit the information stored in their local databases as well as
issue a service request to the upper hierarchy levels by using IEEE
802.11 a/b/g standard (WiFi). The server acts as a repository that
stores both medical evacuation forms and associated events (e.g., a
teleconsulting request). All the actors participating in the diagnostic
or evacuation process may access asynchronously to such repository
and update its content or generate new events. The designed system
pretends to optimise and improve information spreading and flow
among all the system components with the aim of improving both
diagnostic quality and evacuation process.
Abstract: In MPEG and H.26x standards, to eliminate the
temporal redundancy we use motion estimation. Given that the
motion estimation stage is very complex in terms of computational
effort, a hardware implementation on a re-configurable circuit is
crucial for the requirements of different real time multimedia
applications. In this paper, we present hardware architecture for
motion estimation based on "Full Search Block Matching" (FSBM)
algorithm. This architecture presents minimum latency, maximum
throughput, full utilization of hardware resources such as embedded
memory blocks, and combining both pipelining and parallel
processing techniques. Our design is described in VHDL language,
verified by simulation and implemented in a Stratix II
EP2S130F1020C4 FPGA circuit. The experiment result show that the
optimum operating clock frequency of the proposed design is 89MHz
which achieves 160M pixels/sec.
Abstract: A healthcare monitoring system is presented in this
paper. This system is based on ultra-low power sensor nodes and a
personal server, which is based on hardware and software extensions
to a Personal Digital Assistant (PDA)/Smartphone. The sensor node
collects data from the body of a patient and sends it to the personal
server where the data is processed, displayed and made ready to be
sent to a healthcare network, if necessary. The personal server
consists of a compact low power receiver module and equipped with
a Smartphone software. The receiver module takes less than 30 × 30
mm board size and consumes approximately 25 mA in active mode.
Abstract: Parallel programming models exist as an abstraction
of hardware and memory architectures. There are several parallel
programming models in commonly use; they are shared memory
model, thread model, message passing model, data parallel model,
hybrid model, Flynn-s models, embarrassingly parallel computations
model, pipelined computations model. These models are not specific
to a particular type of machine or memory architecture. This paper
expresses the model program for concurrent approach to data parallel
model through java programming.
Abstract: Sharing the manufacturing facility through remote
operation and monitoring of a machining process is challenge for
effective use the production facility. Several automation tools in term
of hardware and software are necessary for successfully remote
operation of a machine. This paper presents a prototype of workpiece
holding attachment for remote operation of milling process by self
configuration the workpiece setup. The prototype is designed with
mechanism to reorient the work surface into machining spindle
direction with high positioning accuracy. Variety of parts geometry
is hold by attachment to perform single setup machining. Pin type
with array pattern additionally clamps the workpiece surface from
two opposite directions for increasing the machining rigidity.
Optimum pins configuration for conforming the workpiece geometry
with minimum deformation is determined through hybrid algorithms,
Genetic Algorithms (GA) and Particle Swarm Optimization (PSO).
Prototype with intelligent optimization technique enables to hold
several variety of workpiece geometry which is suitable for
machining low of repetitive production in remote operation.
Abstract: Safety instrumented systems (SISs) are becoming
increasingly complex and the proportion of programmable electronic
parts is growing. The IEC 61508 global standard was established to
ensure the functional safety of SISs, but it was expressed in highly
macroscopic terms. This study introduces an evaluation process for
hardware safety integrity levels through failure modes, effects, and
diagnostic analysis (FMEDA).FMEDA is widely used to evaluate
safety levels, and it provides the information on failure rates and
failure mode distributions necessary to calculate a diagnostic coverage
factor for a given component. In our evaluation process, the
components of the SIS subsystem are first defined in terms of failure
modes and effects. Then, the failure rate and failure mechanism
distribution are assigned to each component. The safety mode and
detectability of each failure mode are determined for each component.
Finally, the hardware safety integrity level is evaluated based on the
calculated results.
Abstract: Faults in a network may take various forms such as hardware/software errors, vertex/edge faults, etc. Folded hypercube is a well-known variation of the hypercube structure and can be constructed from a hypercube by adding a link to every pair of nodes with complementary addresses. Let FFv (respectively, FFe) be the set of faulty nodes (respectively, faulty links) in an n-dimensional folded hypercube FQn. Hsieh et al. have shown that FQn - FFv - FFe for n ≥ 3 contains a fault-free cycle of length at least 2n -2|FFv|, under the constraints that (1) |FFv| + |FFe| ≤ 2n - 4 and (2) every node in FQn is incident to at least two fault-free links. In this paper, we further consider the constraints |FFv| + |FFe| ≤ 2n - 3. We prove that FQn - FFv - FFe for n ≥ 5 still has a fault-free cycle of length at least 2n - 2|FFv|, under the constraints : (1) |FFv| + |FFe| ≤ 2n - 3, (2) |FFe| ≥ n + 2, and (3) every vertex is still incident with at least two links.
Abstract: Groundwater resources in Arsanjan plain provide
water for agriculture, industry, and human consumption. Continued
agricultural development in this area needs to additional groundwater
resources for, particularly during of drought periods, and effects on
the quantity and quality of ground water available. The purpose of
this study is to evaluate water level changes in the aquifer of
Arsanjan plain in the Fars province in order to determine the areas of
greatest depletion and the causes of depletion. In this plain, farmers
and other users are pumping groundwater faster than its natural
replenishment rate, causing a continuous drop in groundwater tables
and depletion of this resource. In this research variation of
groundwater level, their effects and ways to help control groundwater
levels in aquifer of the Arsanjan plains were evaluated .Excessive
exploitation of groundwater in this aquifer caused the groundwater
levels fall too fast or to unacceptable levels. The average drawdown
of the groundwater level in this plain were 19.66 meters during
1996 to 2003.
Abstract: Lake Nasser is one of the largest reservoirs in the
world. Over 120 million metric tons of sediments are deposited in its
dead storage zone every year. The main objective of the present work
was to determine the physical and chemical characteristics of Lake
Nasser sediments. The sample had a relatively low surface area of 2.9
m2/g which increased more than 3-fold upon chemical activation. The
main chemical elements of the raw sediments were C, O and Si with
some traces of Al, Fe and Ca. The organic functional groups for the
tested sample included O-H, C=C, C-H and C-O, with indications of
Si-O and other metal-C and/or metal-O bonds normally associated
with clayey materials. Potentiometric titration of the sample in
different ionic strength backgrounds revealed an alkaline material with
very strong positive surface charge at pH values just a little less than
the pH of zero charge which is ~9. Surface interactions of the
sediments with the background electrolyte were significant. An
advanced surface complexation model was able to capture these
effects, employing a single-site approach to represent protolysis
reactions in aqueous solution, and to determine the significant surface
species in the pH range of environmental interest.
Abstract: Face detection and recognition has many applications
in a variety of fields such as security system, videoconferencing and
identification. Face classification is currently implemented in
software. A hardware implementation allows real-time processing,
but has higher cost and time to-market.
The objective of this work is to implement a classifier based on
neural networks MLP (Multi-layer Perceptron) for face detection.
The MLP is used to classify face and non-face patterns. The systm is
described using C language on a P4 (2.4 Ghz) to extract weight
values. Then a Hardware implementation is achieved using VHDL
based Methodology. We target Xilinx FPGA as the implementation
support.
Abstract: In this paper, parallel interface for microprocessor
trainer was implemented. A programmable parallel–port device such
as the IC 8255A is initialized for simple input or output and for
handshake input or output by choosing kinds of modes. The hardware
connections and the programs can be used to interface
microprocessor trainer and a personal computer by using IC 8255A.
The assembly programs edited on PC-s editor can be downloaded to
the trainer.
Abstract: Distributed Computing Systems are usually considered the most suitable model for practical solutions of many parallel algorithms. In this paper an enhanced distributed system is presented to improve the time complexity of Binary Indexed Trees (BIT). The proposed system uses multi-uniform processors with identical architectures and a specially designed distributed memory system. The analysis of this system has shown that it has reduced the time complexity of the read query to O(Log(Log(N))), and the update query to constant complexity, while the naive solution has a time complexity of O(Log(N)) for both queries. The system was implemented and simulated using VHDL and Verilog Hardware Description Languages, with xilinx ISE 10.1, as the development environment and ModelSim 6.1c, similarly as the simulation tool. The simulation has shown that the overhead resulting by the wiring and communication between the system fragments could be fairly neglected, which makes it applicable to practically reach the maximum speed up offered by the proposed model.
Abstract: A novel low-cost impedance control structure is
proposed for monitoring the contact force between end-effector and
environment without installing an expensive force/torque sensor.
Theoretically, the end-effector contact force can be estimated from the
superposition of each joint control torque. There have a nonlinear
matrix mapping function between each joint motor control input and
end-effector actuating force/torques vector. This new force control
structure can be implemented based on this estimated mapping matrix.
First, the robot end-effector is manipulated to specified positions, then
the force controller is actuated based on the hall sensor current
feedback of each joint motor. The model-free fuzzy sliding mode
control (FSMC) strategy is employed to design the position and force
controllers, respectively. All the hardware circuits and software
control programs are designed on an Altera Nios II embedded
development kit to constitute an embedded system structure for a
retrofitted Mitsubishi 5 DOF robot. Experimental results show that PI
and FSMC force control algorithms can achieve reasonable contact
force monitoring objective based on this hardware control structure.