VLSI Design of 2-D Discrete Wavelet Transform for Area-Efficient and High-Speed Image Computing
This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.
[1] Mallat, S.: A Theory for Multiresolution Signal Decomposition: The
Wavelet Representation. IEEE Trans. on Pattern Analysis and Machine
Intelligence, Vol. 11, No. 7. (1989) 674-693.
[2] Gnavi, S., Penna, B., Grangetto, M., Magli, E., Olmo, G.: Wavelet
kernels on a DSP: A comparison between lifting and filter banks for
image coding. Applied Signal Processing: Special Issue on
Implementation of DSP and Communication Systems. Vol. 2002. No. 9.
(2002) 981-989.
[3] Daubechies, I., Sweldens, W.: Factoring wavelet transforms into lifting
schemes. The Journal of Fourier Analysis and Applications. vol. 4.
(1998) 247-269.
[4] Acharya, T., Tsai, P.S.: JPEG2000 Standard for Image Compression. A
John Wiley & Sons, Inc. USA (2005).
[5] Andra, K., Chakrabarti, C, Acharya,T.: A VLSI Architecture for Lifting-
Based Forward and Inverse Wavelet Transform. IEEE Transactions on
Signal Processing, vol. 50. No. 4. (2002) 966-977.
[6] Andra, K., Acharya,T., Chakrabarti, C.: A High- Performance JPEG2000
Architecture. IEEE Transactions on Circuits and Systems for Video
Technology, vol. 13. No. 3. (2003) 209-218.
[7] B.-F.Wu and C.-F. Lin, "An efficient architecture for JPEG2000
coprocessor," IEEE Trans. Consum. Electron., vol. 50, no. 4, pp. 1183-
1189, Nov. 2004.
[8] H.-C. Fang, C.-T. Huang, Y.-W. Chang, T.-C.Wang, P.-C. Tseng, C.-J.
Lian, and L.-G. Chen, "81 MS/s JPEG2000 single-chip encoder with
rate-distortion optimization," in Proc. ISSCC Tech. Dig., 2004, vol. 1,
pp. 28-531.
[9] Q. P. Huang, R. Z. Zhou, and Z. L. Hong, "Low memory and low
complexity VLSI implementation of JPEG2000 codec," IEEE Trans.
Consum. Electron., vol. 50, no. 2, pp. 638-646, May 2004.
[10] Descampe, A, et al: A Flexible, Hardware JPEG 2000 Decoder for
Digital Cinema. IEEE Transactions on Circuits and Systems for Video
Technology, Vol. 16, No 11. (2006) 1397-1410.
[11] K. Z. Mei, N. N. Zheng, C. Huang, Y. Liu, and Q. Zeng "VLSI Design
of a High-Speed and Area-Efficient JPEG2000 Encoder," IEEE Trans.
Circuits Syst. Video Technol., vol. 17, no. 8, pp. 1065-1078, Agu. 2007.
[12] JPEG2000 Decoder: BA109JPEG2000D Factsheet.Barco-Silex. (2008).
[13] JPEG 2000 Video CODEC (ADV212). Analog Devices. (2008).
[14] CS6510 JPEG2000 Encoder Amphion Inc. [Online]. Available:
http://www.amphion.com
[15] Acharya, T., Chen, P.: VLSI Implementation of a DWT Architecture.
Proceedings of the IEEE International Symposium on Circuits and
Systems (ISCAS). Monterey, CA. (1998).
[16] Acharya, T.: Architecture for Computing a Two-Dimensional Discrete
Wavelet Transform. US Patent 6178269. (2001).
[17] N.D. Zervas, G.P. Anagnostopoulos, V. Spiliotopoulos, Y.
Andreopoulos, C.E. Goutis, "Evaluation of design alternatives for the 2-
D-discrete wavelet transform," IEEE Trans. Circuits Syst. Video
Technol., Vol.11, no. 12, pp. 1246-1262. Dec. 2001.
[18] G. Dimitroulakos, M.D. Galanis, A. Milidonis, and C.E. Goutis, "A
high-throughput, memory efficient architecture for computing the tilebased
2D discrete wavelet transform for the JPEG2000,"
INTEGRATION, the VLSI journal., vol. 39, no. 1, pp. 1-11, 2005.
[19] VirtexTM-II platform FPGAs: Complete Data Sheet. Xilinx. (2007).
[1] Mallat, S.: A Theory for Multiresolution Signal Decomposition: The
Wavelet Representation. IEEE Trans. on Pattern Analysis and Machine
Intelligence, Vol. 11, No. 7. (1989) 674-693.
[2] Gnavi, S., Penna, B., Grangetto, M., Magli, E., Olmo, G.: Wavelet
kernels on a DSP: A comparison between lifting and filter banks for
image coding. Applied Signal Processing: Special Issue on
Implementation of DSP and Communication Systems. Vol. 2002. No. 9.
(2002) 981-989.
[3] Daubechies, I., Sweldens, W.: Factoring wavelet transforms into lifting
schemes. The Journal of Fourier Analysis and Applications. vol. 4.
(1998) 247-269.
[4] Acharya, T., Tsai, P.S.: JPEG2000 Standard for Image Compression. A
John Wiley & Sons, Inc. USA (2005).
[5] Andra, K., Chakrabarti, C, Acharya,T.: A VLSI Architecture for Lifting-
Based Forward and Inverse Wavelet Transform. IEEE Transactions on
Signal Processing, vol. 50. No. 4. (2002) 966-977.
[6] Andra, K., Acharya,T., Chakrabarti, C.: A High- Performance JPEG2000
Architecture. IEEE Transactions on Circuits and Systems for Video
Technology, vol. 13. No. 3. (2003) 209-218.
[7] B.-F.Wu and C.-F. Lin, "An efficient architecture for JPEG2000
coprocessor," IEEE Trans. Consum. Electron., vol. 50, no. 4, pp. 1183-
1189, Nov. 2004.
[8] H.-C. Fang, C.-T. Huang, Y.-W. Chang, T.-C.Wang, P.-C. Tseng, C.-J.
Lian, and L.-G. Chen, "81 MS/s JPEG2000 single-chip encoder with
rate-distortion optimization," in Proc. ISSCC Tech. Dig., 2004, vol. 1,
pp. 28-531.
[9] Q. P. Huang, R. Z. Zhou, and Z. L. Hong, "Low memory and low
complexity VLSI implementation of JPEG2000 codec," IEEE Trans.
Consum. Electron., vol. 50, no. 2, pp. 638-646, May 2004.
[10] Descampe, A, et al: A Flexible, Hardware JPEG 2000 Decoder for
Digital Cinema. IEEE Transactions on Circuits and Systems for Video
Technology, Vol. 16, No 11. (2006) 1397-1410.
[11] K. Z. Mei, N. N. Zheng, C. Huang, Y. Liu, and Q. Zeng "VLSI Design
of a High-Speed and Area-Efficient JPEG2000 Encoder," IEEE Trans.
Circuits Syst. Video Technol., vol. 17, no. 8, pp. 1065-1078, Agu. 2007.
[12] JPEG2000 Decoder: BA109JPEG2000D Factsheet.Barco-Silex. (2008).
[13] JPEG 2000 Video CODEC (ADV212). Analog Devices. (2008).
[14] CS6510 JPEG2000 Encoder Amphion Inc. [Online]. Available:
http://www.amphion.com
[15] Acharya, T., Chen, P.: VLSI Implementation of a DWT Architecture.
Proceedings of the IEEE International Symposium on Circuits and
Systems (ISCAS). Monterey, CA. (1998).
[16] Acharya, T.: Architecture for Computing a Two-Dimensional Discrete
Wavelet Transform. US Patent 6178269. (2001).
[17] N.D. Zervas, G.P. Anagnostopoulos, V. Spiliotopoulos, Y.
Andreopoulos, C.E. Goutis, "Evaluation of design alternatives for the 2-
D-discrete wavelet transform," IEEE Trans. Circuits Syst. Video
Technol., Vol.11, no. 12, pp. 1246-1262. Dec. 2001.
[18] G. Dimitroulakos, M.D. Galanis, A. Milidonis, and C.E. Goutis, "A
high-throughput, memory efficient architecture for computing the tilebased
2D discrete wavelet transform for the JPEG2000,"
INTEGRATION, the VLSI journal., vol. 39, no. 1, pp. 1-11, 2005.
[19] VirtexTM-II platform FPGAs: Complete Data Sheet. Xilinx. (2007).
@article{"International Journal of Information, Control and Computer Sciences:55219", author = "Mountassar Maamoun and Mehdi Neggazi and Abdelhamid Meraghni and Daoud Berkani", title = "VLSI Design of 2-D Discrete Wavelet Transform for Area-Efficient and High-Speed Image Computing", abstract = "This paper presents a VLSI design approach of a highspeed
and real-time 2-D Discrete Wavelet Transform computing. The
proposed architecture, based on new and fast convolution approach,
reduces the hardware complexity in addition to reduce the critical
path to the multiplier delay. Furthermore, an advanced twodimensional
(2-D) discrete wavelet transform (DWT)
implementation, with an efficient memory area, is designed to
produce one output in every clock cycle. As a result, a very highspeed
is attained. The system is verified, using JPEG2000
coefficients filters, on Xilinx Virtex-II Field Programmable Gate
Array (FPGA) device without accessing any external memory. The
resulting computing rate is up to 270 M samples/s and the (9,7) 2-D
wavelet filter uses only 18 kb of memory (16 kb of first-in-first-out
memory) with 256×256 image size. In this way, the developed design
requests reduced memory and provide very high-speed processing as
well as high PSNR quality.", keywords = "Discrete Wavelet Transform (DWT), Fast
Convolution, FPGA, VLSI.", volume = "2", number = "9", pages = "3005-6", }
