Abstract: Utilization of diverse germplasm is needed to enhance
the genetic diversity of cultivars. The objective of this study was to
evaluate the genetic relationships of 98 alfalfa germplasm accessions
using morphological traits and SSR markers. From the 98 tested
populations, 81 were locals originating in Europe, 17 were introduced
from USA, Australia, New Zealand and Canada. Three primers
generated 67 polymorphic bands. The average polymorphic
information content (PIC) was very high (> 0.90) over all three used
primer combinations. Cluster analysis using Unweighted Pair Group
Method with Arithmetic Means (UPGMA) and Jaccard´s coefficient
grouped the accessions into 2 major clusters with 4 sub-clusters with
no correlation between genetic and morphological diversity. The SSR
analysis clearly indicated that even with three polymorphic primers,
reliable estimation of genetic diversity could be obtained.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: In general fuzzy sets are used to analyze the fuzzy
system reliability. Here intuitionistic fuzzy set theory for analyzing
the fuzzy system reliability has been used. To analyze the fuzzy
system reliability, the reliability of each component of the system as
a triangular intuitionistic fuzzy number is considered. Triangular
intuitionistic fuzzy number and their arithmetic operations are
introduced. Expressions for computing the fuzzy reliability of a
series system and a parallel system following triangular intuitionistic
fuzzy numbers have been described. Here an imprecise reliability
model of an electric network model of dark room is taken. To
compute the imprecise reliability of the above said system, reliability
of each component of the systems is represented by triangular
intuitionistic fuzzy numbers. Respective numerical example is
presented.
Abstract: Adopting the measured constitutive relationship of
stress-strain of river ice, the finite element analysis model of
percussive force of river ice and pier is established, by the explicit
dynamical analysis software package LS-DYNA. Effects of element
types, contact method and arithmetic of ice and pier, coupled modes
between different elements, mesh density of pier, and ice sheet in
contact area on the collision force are studied. Some of measures for
the collision force analysis of river ice and pier are proposed as
follows: bridge girder can adopt beam161 element with 3-node; pier
below the line of 1.30m above ice surface and ice sheet use solid164
element with 8-node; in order to accomplish the connection of
different elements, the rigid body with 0.01-0.05m thickness is defined
between solid164 and beam161; the contact type of ice and pier adopts
AUTOMATIC_SURFACE_TO_SURFACE, using symmetrical
penalty function algorithms; meshing size of pier below the line of
1.30m above ice surface should not less than 0.25×0.25×0.5m3. The
simulation results have the advantage of high precision by making a
comparison between measured and computed data. The research
results can be referred for collision force study between river ice and
pier.
Abstract: In-place sorting algorithms play an important role in many fields such as very large database systems, data warehouses, data mining, etc. Such algorithms maximize the size of data that can be processed in main memory without input/output operations. In this paper, a novel in-place sorting algorithm is presented. The algorithm comprises two phases; rearranging the input unsorted array in place, resulting segments that are ordered relative to each other but whose elements are yet to be sorted. The first phase requires linear time, while, in the second phase, elements of each segment are sorted inplace in the order of z log (z), where z is the size of the segment, and O(1) auxiliary storage. The algorithm performs, in the worst case, for an array of size n, an O(n log z) element comparisons and O(n log z) element moves. Further, no auxiliary arithmetic operations with indices are required. Besides these theoretical achievements of this algorithm, it is of practical interest, because of its simplicity. Experimental results also show that it outperforms other in-place sorting algorithms. Finally, the analysis of time and space complexity, and required number of moves are presented, along with the auxiliary storage requirements of the proposed algorithm.
Abstract: A given polynomial, possibly with multiple roots, is
factored into several lower-degree distinct-root polynomials with
natural-order-integer powers. All the roots, including multiplicities,
of the original polynomial may be obtained by solving these lowerdegree
distinct-root polynomials, instead of the original high-degree
multiple-root polynomial directly.
The approach requires polynomial Greatest Common Divisor
(GCD) computation. The very simple and effective process, “Monic
polynomial subtractions" converted trickily from “Longhand
polynomial divisions" of Euclidean algorithm is employed. It
requires only simple elementary arithmetic operations without any
advanced mathematics.
Amazingly, the derived routine gives the expected results for the
test polynomials of very high degree, such as p( x) =(x+1)1000.
Abstract: New methodologies for XOR-XNOR circuits are
proposed to improve the speed and power as these circuits are basic
building blocks of many arithmetic circuits. This paper evaluates and
compares the performance of various XOR-XNOR circuits. The
performance of the XOR-XNOR circuits based on TSMC 0.18μm
process models at all range of the supply voltage starting from 0.6V
to 3.3V is evaluated by the comparison of the simulation results
obtained from HSPICE. Simulation results reveal that the proposed
circuit exhibit lower PDP and EDP, more power efficient and faster
when compared with best available XOR-XNOR circuits in the
literature.
Abstract: This paper presents an adaptive technique for generation
of data required for construction of artificial neural network-based
performance model of nano-scale CMOS inverter circuit. The training
data are generated from the samples through SPICE simulation. The
proposed algorithm has been compared to standard progressive sampling
algorithms like arithmetic sampling and geometric sampling.
The advantages of the present approach over the others have been
demonstrated. The ANN predicted results have been compared with
actual SPICE results. A very good accuracy has been obtained.
Abstract: In this paper, a residue number arithmetic is used in
direct sequence spread spectrum system, this system is evaluated and
the bit error probability of this system is compared to that of non
residue number system. The effect of channel bandwidth, PN
sequences, multipath effect and modulation scheme are studied. A
Matlab program is developed to measure the signal-to-noise ratio
(SNR), and the bit error probability for the various schemes.
Abstract: This paper proposes an architecture of dynamically
reconfigurable arithmetic circuit. Dynamic reconfiguration is a
technique to realize required functions by changing hardware
construction during operations. The proposed circuit is based on a
complex number multiply-accumulation circuit which is used
frequently in the field of digital signal processing. In addition, the
proposed circuit performs real number double precision arithmetic
operations. The data formats are single and double precision floating
point number based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: We present a discussion of three adaptive filtering
algorithms well known for their one-step termination property, in
terms of their relationship with the minimal residual method. These
algorithms are the normalized least mean square (NLMS), Affine
Projection algorithm (APA) and the recursive least squares algorithm
(RLS). The NLMS is shown to be a result of the orthogonality
condition imposed on the instantaneous approximation of the Wiener
equation, while APA and RLS algorithm result from orthogonality
condition in multi-dimensional minimal residual formulation. Further
analysis of the minimal residual formulation for the RLS leads to
a triangular system which also possesses the one-step termination
property (in exact arithmetic)
Abstract: Residue Number System (RNS) is a modular representation and is proved to be an instrumental tool in many digital signal processing (DSP) applications which require high-speed computations. RNS is an integer and non weighted number system; it can support parallel, carry-free, high-speed and low power arithmetic. A very interesting correspondence exists between the concepts of Multiple Valued Logic (MVL) and Residue Number Arithmetic. If the number of levels used to represent MVL signals is chosen to be consistent with the moduli which create the finite rings in the RNS, MVL becomes a very natural representation for the RNS. There are two concerns related to the application of this Number System: reaching the most possible speed and the largest dynamic range. There is a conflict when one wants to resolve both these problem. That is augmenting the dynamic range results in reducing the speed in the same time. For achieving the most performance a method is considere named “One-Hot Residue Number System" in this implementation the propagation is only equal to one transistor delay. The problem with this method is the huge increase in the number of transistors they are increased in order m2 . In real application this is practically impossible. In this paper combining the Multiple Valued Logic and One-Hot Residue Number System we represent a new method to resolve both of these two problems. In this paper we represent a novel design of an OHRNS-based adder circuit. This circuit is useable for Multiple Valued Logic moduli, in comparison to other RNS design; this circuit has considerably improved the number of transistors and power consumption.
Abstract: A special case of floating point data representation is block
floating point format where a block of operands are forced to have a joint
exponent term. This paper deals with the finite wordlength properties of
this data format. The theoretical errors associated with the error model for
block floating point quantization process is investigated with the help of error
distribution functions. A fast and easy approximation formula for calculating
signal-to-noise ratio in quantization to block floating point format is derived.
This representation is found to be a useful compromise between fixed point
and floating point format due to its acceptable numerical error properties over
a wide dynamic range.
Abstract: In this study, some physical and mechanical properties
of jujube fruits, were measured and compared at constant moisture
content of 15.5% w.b. The results showed that the mean length, width
and thickness of jujube fruits were 18.88, 16.79 and 15.9 mm,
respectively. The mean projected areas of jujube perpendicular to
length, width, and thickness were 147.01, 224.08 and 274.60 mm2,
respectively. The mean mass and volume were 1.51 g and 2672.80
mm3, respectively. The arithmetic mean diameter, geometric mean
diameter and equivalent diameter varied from 14.53 to 20 mm, 14.5
to 19.94 mm, and 14.52 to 19.97 mm, respectively. The sphericity,
aspect ratio and surface area of jujube fruits were 0.91, 0.89 and
926.28 mm2, respectively. Whole fruit density, bulk density and
porosity of jujube fruits were measured and found to be 1.52 g/cm3,
0.3 g/cm3 and 79.3%, respectively. The angle of repose of jujube fruit
was 14.66° (±0.58°). The static coefficient of friction on galvanized
iron steel was higher than that on plywood and lower than that on
glass surface. The values of rupture force, deformation, hardness and
energy absorbed were found to be between 11.13-19.91N, 2.53-
4.82mm, 3.06-5.81N mm and 20.13-39.08 N/mm, respectively.
Abstract: By using a new set of arithmetic operations on interval numbers, we discuss some arithmetic properties of interval matrices which intern helps us to compute the powers of interval matrices and to solve the system of interval linear equations.
Abstract: This paper presented two new efficient algorithms
for contour approximation. The proposed algorithm is compared
with Ramer (good quality), Triangle (faster) and Trapezoid (fastest)
in this work; which are briefly described. Cartesian co-ordinates of
an input contour are processed in such a manner that finally
contours is presented by a set of selected vertices of the edge of the
contour. In the paper the main idea of the analyzed procedures for
contour compression is performed. For comparison, the mean
square error and signal-to-noise ratio criterions are used.
Computational time of analyzed methods is estimated depending on
a number of numerical operations. Experimental results are
obtained both in terms of image quality, compression ratios, and
speed. The main advantages of the analyzed algorithm is small
numbers of the arithmetic operations compared to the existing
algorithms.
Abstract: In this work a new method for low complexity
image coding is presented, that permits different settings and great
scalability in the generation of the final bit stream. This coding
presents a continuous-tone still image compression system that
groups loss and lossless compression making use of finite arithmetic
reversible transforms. Both transformation in the space of color and
wavelet transformation are reversible. The transformed coefficients
are coded by means of a coding system in depending on a
subdivision into smaller components (CFDS) similar to the bit
importance codification. The subcomponents so obtained are
reordered by means of a highly configure alignment system
depending on the application that makes possible the re-configure of
the elements of the image and obtaining different importance levels
from which the bit stream will be generated. The subcomponents of
each importance level are coded using a variable length entropy
coding system (VBLm) that permits the generation of an embedded
bit stream. This bit stream supposes itself a bit stream that codes a
compressed still image. However, the use of a packing system on the
bit stream after the VBLm allows the realization of a final highly
scalable bit stream from a basic image level and one or several
improvement levels.
Abstract: The voice signal in Voice over Internet protocol (VoIP) system is processed through the best effort policy based IP network, which leads to the network degradations including delay, packet loss jitter. The work in this paper presents the implementation of finite impulse response (FIR) filter for voice quality improvement in the VoIP system through distributed arithmetic (DA) algorithm. The VoIP simulations are conducted with AMR-NB 6.70 kbps and G.729a speech coders at different packet loss rates and the performance of the enhanced VoIP signal is evaluated using the perceptual evaluation of speech quality (PESQ) measurement for narrowband signal. The results show reduction in the computational complexity in the system and significant improvement in the quality of the VoIP voice signal.
Abstract: This paper makes an attempt to solve the problem of
searching and retrieving of similar MRI photos via Internet services
using morphological features which are sourced via the original
image. This study is aiming to be considered as an additional tool of
searching and retrieve methods. Until now the main way of the
searching mechanism is based on the syntactic way using keywords.
The technique it proposes aims to serve the new requirements of
libraries. One of these is the development of computational tools for
the control and preservation of the intellectual property of digital
objects, and especially of digital images. For this purpose, this paper
proposes the use of a serial number extracted by using a previously
tested semantic properties method. This method, with its center being
the multi-layers of a set of arithmetic points, assures the following
two properties: the uniqueness of the final extracted number and the
semantic dependence of this number on the image used as the
method-s input. The major advantage of this method is that it can
control the authentication of a published image or its partial
modification to a reliable degree. Also, it acquires the better of the
known Hash functions that the digital signature schemes use and
produces alphanumeric strings for cases of authentication checking,
and the degree of similarity between an unknown image and an
original image.
Abstract: According to the density of the chips, designers are
trying to put so any facilities of computational and storage on single
chips. Along with the complexity of computational and storage
circuits, the designing, testing and debugging become more and more
complex and expensive. So, hardware design will be built by using
very high speed hardware description language, which is more
efficient and cost effective. This paper will focus on the
implementation of 32-bit ALU design based on Verilog hardware
description language. Adder and subtracter operate correctly on both
unsigned and positive numbers. In ALU, addition takes most of the
time if it uses the ripple-carry adder. The general strategy for
designing fast adders is to reduce the time required to form carry
signals. Adders that use this principle are called carry look- ahead
adder. The carry look-ahead adder is to be designed with combination
of 4-bit adders. The syntax of Verilog HDL is similar to the C
programming language. This paper proposes a unified approach to
ALU design in which both simulation and formal verification can
co-exist.