Abstract: Error correcting codes are used for detection and correction of errors in digital communication system. Error correcting coding is based on appending of redundancy to the information message according to a prescribed algorithm. Reed Solomon codes are part of channel coding and withstand the effect of noise, interference and fading. Galois field arithmetic is used for encoding and decoding reed Solomon codes. Galois field multipliers and linear feedback shift registers are used for encoding the information data block. The design of Reed Solomon encoder is complex because of use of LFSR and Galois field arithmetic. The purpose of this paper is to design and implement Reed Solomon (255, 239) encoder with optimized and lesser number of Galois Field multipliers. Symmetric generator polynomial is used to reduce the number of GF multipliers. To increase the capability toward error correction, convolution interleaving will be used with RS encoder. The Design will be implemented on Xilinx FPGA Spartan II.
Abstract: The residue number system (RNS) is popular in high performance computation applications because of its carry-free nature. The challenges of RNS systems design lie in the moduli set selection and in the reverse conversion from residue representation to weighted representation. In this paper, we proposed a fully parallel reverse conversion algorithm for the moduli set {rn - 2, rn - 1, rn}, based on simple mathematical relationships. Also an efficient hardware realization of this algorithm is presented. Our proposed converter is very faster and results to hardware savings, compared to the other reverse converters.
Abstract: This paper presents a new Quality-Controlled, wavelet based, compression method for electrocardiogram (ECG) signals. Initially, an ECG signal is decomposed using the wavelet transform. Then, the resulting coefficients are iteratively thresholded to guarantee that a predefined goal percent root mean square difference (GPRD) is matched within tolerable boundaries. The quantization strategy of extracted non-zero wavelet coefficients (NZWC), according to the combination of RLE, HUFFMAN and arithmetic encoding of the NZWC and a resulting look up table, allow the accomplishment of high compression ratios with good quality reconstructed signals.
Abstract: This paper has, as its point of departure, the foundational
axiomatic theory of E. De Giorgi (1996, Scuola Normale
Superiore di Pisa, Preprints di Matematica 26, 1), based on two
primitive notions of quality and relation. With the introduction of
a unary relation, we develop a system totally based on the sole
primitive notion of relation. Such a modification enables a definition
of the concept of dynamic unary relation. In this way we construct a
simple language capable to express other well known theories such
as Robinson-s arithmetic or a piece of a theory of concatenation. A
key role in this system plays an abstract relation designated by “( )",
which can be interpreted in different ways, but in this paper we will
focus on the case when we can perform computations and obtain
results.
Abstract: Different types of aggregation operators such as the
ordered weighted quasi-arithmetic mean (Quasi-OWA) operator and
the normalized Hamming distance are studied. We introduce the use
of the OWA operator in generalized distances such as the quasiarithmetic
distance. We will call these new distance aggregation the
ordered weighted quasi-arithmetic distance (Quasi-OWAD) operator.
We develop a general overview of this type of generalization and
study some of their main properties such as the distinction between
descending and ascending orders. We also consider different families
of Quasi-OWAD operators such as the Minkowski ordered weighted
averaging distance (MOWAD) operator, the ordered weighted
averaging distance (OWAD) operator, the Euclidean ordered
weighted averaging distance (EOWAD) operator, the normalized
quasi-arithmetic distance, etc.
Abstract: We present the induced generalized hybrid
averaging (IGHA) operator. It is a new aggregation operator
that generalizes the hybrid averaging (HA) by using
generalized means and order inducing variables. With this
formulation, we get a wide range of mean operators such as
the induced HA (IHA), the induced hybrid quadratic
averaging (IHQA), the HA, etc. The ordered weighted
averaging (OWA) operator and the weighted average (WA)
are included as special cases of the HA operator. Therefore,
with this generalization we can obtain a wide range of
aggregation operators such as the induced generalized OWA
(IGOWA), the generalized OWA (GOWA), etc. We further
generalize the IGHA operator by using quasi-arithmetic
means. Then, we get the Quasi-IHA operator. Finally, we also
develop an illustrative example of the new approach in a
financial decision making problem. The main advantage of the
IGHA is that it gives a more complete view of the decision
problem to the decision maker because it considers a wide
range of situations depending on the operator used.
Abstract: Efficient modulo 2n+1 adders are important for
several applications including residue number system, digital signal
processors and cryptography algorithms. In this paper we present a
novel modulo 2n+1 addition algorithm for a recently represented
number system. The proposed approach is introduced for the
reduction of the power dissipated. In a conventional modulo 2n+1
adder, all operands have (n+1)-bit length. To avoid using (n+1)-bit
circuits, the diminished-1 and carry save diminished-1 number
systems can be effectively used in applications. In the paper, we also
derive two new architectures for designing modulo 2n+1 adder, based
on n-bit ripple-carry adder. The first architecture is a faster design
whereas the second one uses less hardware. In the proposed method,
the special treatment required for zero operands in Diminished-1
number system is removed. In the fastest modulo 2n+1 adders in
normal binary system, there are 3-operand adders. This problem is
also resolved in this paper. The proposed architectures are compared
with some efficient adders based on ripple-carry adder and highspeed
adder. It is shown that the hardware overhead and power
consumption will be reduced. As well as power reduction, in some
cases, power-delay product will be also reduced.
Abstract: This paper To get the angle value with a MEMS rate
gyroscope in some specific field, the usual method is to make an
integral operation to the rate output, which will lead the error
cumulating effect. So the rate gyro is not suitable. MEMS rate
integrating gyroscope (MRIG) will solve this problem. A DSP system
has been developed to implement the control arithmetic. The system
can measure the angle of rotation directly by the control loops that
make the sensor work in whole-angle mode. Modeling the system with
MATLAB, desirable results of angle outputs are got, which prove the
feasibility of the control arithmetic.
Abstract: Compression algorithms reduce the redundancy in
data representation to decrease the storage required for that data.
Lossless compression researchers have developed highly
sophisticated approaches, such as Huffman encoding, arithmetic
encoding, the Lempel-Ziv (LZ) family, Dynamic Markov
Compression (DMC), Prediction by Partial Matching (PPM), and
Burrows-Wheeler Transform (BWT) based algorithms.
Decompression is also required to retrieve the original data by
lossless means. A compression scheme for text files coupled with
the principle of dynamic decompression, which decompresses only
the section of the compressed text file required by the user instead of
decompressing the entire text file. Dynamic decompressed files offer
better disk space utilization due to higher compression ratios
compared to most of the currently available text file formats.
Abstract: In this work, we study elliptic divisibility sequences
over finite fields. Morgan Ward in [14], [15] gave arithmetic theory
of elliptic divisibility sequences and formulas for elliptic divisibility
sequences with rank two over finite field Fp. We study elliptic
divisibility sequences with rank three, four and five over a finite field
Fp, where p > 3 is a prime and give general terms of these sequences
and then we determine elliptic and singular curves associated with
these sequences.
Abstract: Among various testing methodologies, Built-in Self-
Test (BIST) is recognized as a low cost, effective paradigm. Also,
full adders are one of the basic building blocks of most arithmetic
circuits in all processing units. In this paper, an optimized testable 2-
bit full adder as a test building block is proposed. Then, a BIST
procedure is introduced to scale up the building block and to generate
a self testable n-bit full adders. The target design can achieve 100%
fault coverage using insignificant amount of hardware redundancy.
Moreover, Overall test time is reduced by utilizing polymorphic
gates and also by testing full adder building blocks in parallel.
Abstract: Designing and implementing intelligent systems has become a crucial factor for the innovation and development of better products of space technologies. A neural network is a parallel system, capable of resolving paradigms that linear computing cannot. Field programmable gate array (FPGA) is a digital device that owns reprogrammable properties and robust flexibility. For the neural network based instrument prototype in real time application, conventional specific VLSI neural chip design suffers the limitation in time and cost. With low precision artificial neural network design, FPGAs have higher speed and smaller size for real time application than the VLSI and DSP chips. So, many researchers have made great efforts on the realization of neural network (NN) using FPGA technique. In this paper, an introduction of ANN and FPGA technique are briefly shown. Also, Hardware Description Language (VHDL) code has been proposed to implement ANNs as well as to present simulation results with floating point arithmetic. Synthesis results for ANN controller are developed using Precision RTL. Proposed VHDL implementation creates a flexible, fast method and high degree of parallelism for implementing ANN. The implementation of multi-layer NN using lookup table LUT reduces the resource utilization for implementation and time for execution.
Abstract: This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Abstract: The concept of order reduction by least-squares moment matching and generalised least-squares methods has been extended about a general point ?a?, to obtain the reduced order models for linear, time-invariant dynamic systems. Some heuristic criteria have been employed for selecting the linear shift point ?a?, based upon the means (arithmetic, harmonic and geometric) of real parts of the poles of high order system. It is shown that the resultant model depends critically on the choice of linear shift point ?a?. The validity of the criteria is illustrated by solving a numerical example and the results are compared with the other existing techniques.
Abstract: This paper proposes an efficient finite precision block floating point (BFP) treatment to the fixed coefficient finite impulse response (FIR) digital filter. The treatment includes effective implementation of all the three forms of the conventional FIR filters, namely, direct form, cascaded and par- allel, and a roundoff error analysis of them in the BFP format. An effective block formatting algorithm together with an adaptive scaling factor is pro- posed to make the realizations more simple from hardware view point. To this end, a generic relation between the tap weight vector length and the input block length is deduced. The implementation scheme also emphasises on a simple block exponent update technique to prevent overflow even during the block to block transition phase. The roundoff noise is also investigated along the analogous lines, taking into consideration these implementational issues. The simulation results show that the BFP roundoff errors depend on the sig- nal level almost in the same way as floating point roundoff noise, resulting in approximately constant signal to noise ratio over a relatively large dynamic range.
Abstract: we propose a new normalized LMS (NLMS) algorithm, which gives satisfactory performance in certain applications in comaprison with con-ventional NLMS recursion. This new algorithm can be treated as a block based simplification of NLMS algorithm with significantly reduced number of multi¬ply and accumulate as well as division operations. It is also shown that such a recursion can be easily implemented in block floating point (BFP) arithmetic, treating the implementational issues much efficiently. In particular, the core challenges of a BFP realization to such adaptive filters are mainly considered in this regard. A global upper bound on the step size control parameter of the new algorithm due to BFP implementation is also proposed to prevent overflow in filtering as well as weight updating operations jointly.
Abstract: As embedded and portable systems were emerged power consumption of circuits had been major challenge. On the other hand latency as determines frequency of circuits is also vital task. Therefore, trade off between both of them will be desirable. Modulo 2n+1 adders are important part of the residue number system (RNS) based arithmetic units with the interesting moduli set (2n-1,2n, 2n+1). In this manuscript we have introduced novel binary representation to the design of modulo 2n+1 adder. VLSI realization of proposed architecture under 180 nm full static CMOS technology reveals its superiority in terms of area, power consumption and power-delay product (PDP) against several peer existing structures.
Abstract: An important task in solving second order linear ordinary differential equations by the finite difference is to choose a suitable stepsize h. In this paper, by using the stochastic arithmetic, the CESTAC method and the CADNA library we present a procedure to estimate the optimal stepsize hopt, the stepsize which minimizes the global error consisting of truncation and round-off error.
Abstract: The residue number system (RNS), due to its
properties, is used in applications in which high performance
computation is needed. The carry free nature, which makes the
arithmetic, carry bounded as well as the paralleling facility is the
reason of its capability of high speed rendering. Since carry is not
propagated between the moduli in this system, the performance is
only restricted by the speed of the operations in each modulus. In this
paper a novel method of number representation by use of redundancy
is suggested in which {rn- 2,rn-1,rn} is the reference moduli set
where r=2k+1 and k =1, 2,3,.. This method achieves fast
computations and conversions and makes the circuits of them much
simpler.
Abstract: The main issue of interest here is whether individuals
who differ in arithmetical reasoning ability and levels of imagery ability display different brain activity during the conduct of mental
arithmetical reasoning tasks. This was a case study of four
participants who represented four extreme combinations of Maths –Imagery abilities: ie., low-low, high-high, high-low, low-high respectively. As the Ps performed a series of 60 arithmetical reasoning tasks, 128-channel EEG recordings were taken and the
pre-response interval subsequently analysed using EGI GeosourceTM
software. The P who was high in both imagery and maths ability
showed peak activity prior to response in BA7 (superior parietal cortex) but other Ps did not show peak activity in this region. The
results are considered in terms of the diverse routes that may be employed by individuals during the conduct of arithmetical reasoning
tasks and the possible implications of this for mathematics education.