Abstract: The residue number system (RNS) is popular in high performance computation applications because of its carry-free nature. The challenges of RNS systems design lie in the moduli set selection and in the reverse conversion from residue representation to weighted representation. In this paper, we proposed a fully parallel reverse conversion algorithm for the moduli set {rn - 2, rn - 1, rn}, based on simple mathematical relationships. Also an efficient hardware realization of this algorithm is presented. Our proposed converter is very faster and results to hardware savings, compared to the other reverse converters.
Abstract: Reversible logic is becoming more and more prominent
as the technology sets higher demands on heat, power, scaling
and stability. Reversible gates are able at any time to "undo" the
current step or function. Multiple-valued logic has the advantage of
transporting and evaluating higher bits each clock cycle than binary.
Moreover, we demonstrate in this paper, combining these disciplines
we can construct powerful multiple-valued reversible logic structures.
In this paper a reversible block implemented by pseudo floatinggate
can perform AD-function and a DA-function as its reverse
application.