Abstract: This paper presents a novel CMOS four-transistor
SRAM cell for very high density and low power embedded SRAM
applications as well as for stand-alone SRAM applications. This cell
retains its data with leakage current and positive feedback without
refresh cycle. The new cell size is 20% smaller than a conventional
six-transistor cell using same design rules. Also proposed cell uses
two word-lines and one pair bit-line. Read operation perform from
one side of cell, and write operation perform from another side of
cell, and swing voltage reduced on word-lines thus dynamic power
during read/write operation reduced. The fabrication process is fully
compatible with high-performance CMOS logic technologies,
because there is no need to integrate a poly-Si resistor or a TFT load.
HSPICE simulation in standard 0.25μm CMOS technology confirms
all results obtained from this paper.
Abstract: With rapid technology scaling, the proportion of the
static power consumption catches up with dynamic power
consumption gradually. To decrease leakage consumption is
becoming more and more important in low-power design. This paper
presents a power-gating scheme for P-DTGAL (p-type dual
transmission gate adiabatic logic) circuits to reduce leakage power
dissipations under deep submicron process. The energy dissipations of
P-DTGAL circuits with power-gating scheme are investigated in
different processes, frequencies and active ratios. BSIM4 model is
adopted to reflect the characteristics of the leakage currents. HSPICE
simulations show that the leakage loss is greatly reduced by using the
P-DTGAL with power-gating techniques.
Abstract: In this study, the Taguchi method was used to optimize the effect of HALO structure or halo implant variations on threshold voltage (VTH) and leakage current (ILeak) in 45nm p-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) device. Besides halo implant dose, the other process parameters which used were Source/Drain (S/D) implant dose, oxide growth temperature and silicide anneal temperature. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with Taguchi method to aid in design and optimize the process parameters. In this research, the most effective process parameters with respect to VTH and ILeak are halo implant dose (40%) and S/D implant dose (52%) respectively. Whereas the second ranking factor affecting VTH and ILeak are oxide growth temperature (32%) and halo implant dose (34%) respectively. The results show that after optimizations approaches is -0.157V at ILeak=0.195mA/μm.
Abstract: This paper presents the experimental results of
comparison between leakage currents and discharge currents. The leakage currents were obtained on polluted porcelain insulator.
Whereas, the discharge currents were obtained on lightly artificial
polluted porcelain specimen. The conducted measurements were
leakage current or discharge current and applied voltage. The insulator or specimen was in a hermetically sealed chamber, and the
current waveforms were analyzed using FFT.
The result indicated that the leakage current (LC) on low RH condition the fifth harmonic would be visible, and followed by the
seventh harmonic. The insulator had capacitive property. Otherwise,
on 99% relative humidity, the fifth harmonic would also be visible,
and the phase angle reached up to 12.2 degree. Whereas, on discharge current, the third harmonic would be visible, and followed
by fifth harmonic. The third harmonic would increase as pressure reduced. On this condition, the specimen had a non-linear characteristics
Abstract: This paper presents the experimental results of
leakage current waveforms which appears on porcelain insulator
surface due to existence of artificial pollutants. The tests have been
done using the chemical compounds of NaCl, Na2SiO3, H2SO4, CaO,
Na2SO4, KCl, Al2SO4, MgSO4, FeCl3, and TiO2. The insulator
surface was coated with those compounds and dried. Then, it was
tested in the chamber where the high voltage was applied. Using
correspondence analysis, the result indicated that the fundamental
harmonic of leakage current was very close to the applied voltage
and third harmonic leakage current was close to the yielded leakage
current amplitude. The first harmonic power was correlated to first
harmonic amplitude of leakage current, and third harmonic power
was close to third harmonic one. The chemical compounds of H2SO4
and Na2SiO3 affected to the power factor of around 70%. Both are the
most conductive, due to the power factor drastically increase among
the chemical compounds.
Abstract: In this paper, gate leakage current has been mitigated
by the use of novel nanoscale MOSFET with Source/Drain-to-Gate
Non-overlapped and high-k spacer structure for the first time. A
compact analytical model has been developed to study the gate
leakage behaviour of proposed MOSFET structure. The result
obtained has found good agreement with the Sentaurus Simulation.
Fringing gate electric field through the dielectric spacer induces
inversion layer in the non-overlap region to act as extended S/D
region. It is found that optimal Source/Drain-to-Gate Non-overlapped
and high-k spacer structure has reduced the gate leakage current to
great extent as compared to those of an overlapped structure. Further,
the proposed structure had improved off current, subthreshold slope
and DIBL characteristic. It is concluded that this structure solves the
problem of high leakage current without introducing the extra series
resistance.
Abstract: High performance Resistive Random Access Memory
(RRAM) based on HfOx has been prepared and its temperature
instability has been investigated in this work. With increasing
temperature, it is found that: leakage current at high resistance state
increases, which can be explained by the higher density of traps
inside dielectrics (related to trap-assistant tunneling), leading to a
smaller On/Off ratio; set and reset voltages decrease, which may be
attributed to the higher oxygen ion mobility, in addition to the
reduced potential barrier to create / recover oxygen ions (or oxygen
vacancies); temperature impact on the RRAM retention degradation
is more serious than electrical bias.