Abstract: Selected Mapping (SLM) is a PAPR reduction technique, which converts the OFDM signal into several independent signals by multiplication with the phase sequence set and transmits one of the signals with lowest PAPR. But it requires the index of the selected signal i.e. side information (SI) to be transmitted with each OFDM symbol. The PAPR reduction capability of the SLM scheme depends on the selection of phase sequence set. In this paper, we have proposed a new phase sequence set generation scheme based on M-ary chaotic sequence and a mapping scheme to map quaternary data to concentric circle constellation (CCC) is used. It is shown that this method does not require SI and provides better SER performance with good PAPR reduction capability as compared to existing SLMOFDM methods.
Abstract: Medical compression bandages are widely used in the
treatment of chronic venous disorder. In order to design effective
compression bandages, researchers have attempted to describe the
interface pressure applied by multi-layer bandages using mathematical
models. This paper reports on the work carried out to
compare and validate the mathematical models used to describe the
interface pressure applied by multi-layer bandages. Both analytical
and experimental results showed that using simple multiplication
of a number of bandage layers with the pressure applied by one
layer of bandage or ignoring the increase in the limb radius due to
former layers of bandage will result in overestimating the pressure.
Experimental results showed that the mathematical models, which
take into consideration the increase in the limb radius due to former
bandage layers, are more accurate than the one which does not.
Abstract: This paper describes the pipeline architecture of
high-speed modified Booth multipliers. The proposed multiplier
circuits are based on the modified Booth algorithm and the pipeline
technique which are the most widely used to accelerate the
multiplication speed. In order to implement the optimally pipelined
multipliers, many kinds of experiments have been conducted. The
speed of the multipliers is greatly improved by properly deciding the
number of pipeline stages and the positions for the pipeline registers to
be inserted. We described the proposed modified Booth multiplier
circuits in Verilog HDL and synthesized the gate-level circuits using
0.13um standard cell library. The resultant multiplier circuits show
better performance than others. Since the proposed multipliers operate
at GHz ranges, they can be used in the systems requiring very high
performance.
Abstract: A slant weighted Toeplitz operator Aφ is an operator
on L2(β) defined as Aφ = WMφ where Mφ is the weighted
multiplication operator and W is an operator on L2(β) given by
We2n = βn
β2n
en, {en}n∈Z being the orthonormal basis. In this paper,
we generalise Aφ to the k-th order slant weighted Toeplitz operator
Uφ and study its properties.
Abstract: Full adders are important components in applications
such as digital signal processors (DSP) architectures and
microprocessors. In addition to its main task, which is adding two
numbers, it participates in many other useful operations such as
subtraction, multiplication, division,, address calculation,..etc. In
most of these systems the adder lies in the critical path that
determines the overall speed of the system. So enhancing the
performance of the 1-bit full adder cell (the building block of the
adder) is a significant goal.Demands for the low power VLSI have
been pushing the development of aggressive design methodologies to
reduce the power consumption drastically. To meet the growing
demand, we propose a new low power adder cell by sacrificing the
MOS Transistor count that reduces the serious threshold loss
problem, considerably increases the speed and decreases the power
when compared to the static energy recovery full (SERF) adder. So a
new improved 14T CMOS l-bit full adder cell is presented in this
paper. Results show 50% improvement in threshold loss problem,
45% improvement in speed and considerable power consumption
over the SERF adder and other different types of adders with
comparable performance.
Abstract: Malaria is transmitted to the human by biting of
infected Anopheles mosquitoes. This disease is a serious, acute and
chronic relapsing infection to humans. Fever, nausea, vomiting, back
pain, increased sweating anemia and splenomegaly (enlargement of
the spleen) are the symptoms of the patients who infected with this
disease. It is caused by the multiplication of protozoa parasite of the
genus Plasmodium. Plasmodium falciparum, Plasmodium vivax,
Plasmodium malariae and Plasmodium ovale are the four types of
Plasmodium malaria. A mathematical model for the transmission of
Plasmodium Malaria is developed in which the human and vector
population are divided into two classes, the susceptible and the
infectious classes. In this paper, we formulate the dynamical model
of Plasmodium falciparum and Plasmodium vivax malaria. The
standard dynamical analysis is used for analyzing the behavior for
the transmission of this disease. The Threshold condition is found
and numerical results are shown to confirm the analytical results.
Abstract: In this paper, a novel deinterlacing algorithm is
proposed. The proposed algorithm approximates the distribution of the
luminance into a polynomial function. Instead of using one
polynomial function for all pixels, different polynomial functions are
used for the uniform, texture, and directional edge regions. The
function coefficients for each region are computed by matrix
multiplications. Experimental results demonstrate that the proposed
method performs better than the conventional algorithms.
Abstract: Multiplication algorithms have considerable effect on
processors performance. A new high-speed, low-power
multiplication algorithm has been presented using modified Dadda
tree structure. Three important modifications have been implemented
in inner product generation step, inner product reduction step and
final addition step. Optimized algorithms have to be used into basic
computation components, such as multiplication algorithms. In this
paper, we proposed a new algorithm to reduce power, delay, and
transistor count of a multiplication algorithm implemented using low
power modified counter. This work presents a novel design for
Dadda multiplication algorithms. The proposed multiplication
algorithm includes structured parts, which have important effect on
inner product reduction tree. In this paper, a 1.3V, 64-bit carry hybrid
adder is presented for fast, low voltage applications. The new 64-bit
adder uses a new circuit to implement the proposed carry hybrid
adder. The new adder using 80 nm CMOS technology has been
implemented on 700 MHz clock frequency. The proposed
multiplication algorithm has achieved 14 percent improvement in
transistor count, 13 percent reduction in delay and 12 percent
modification in power consumption in compared with conventional
designs.
Abstract: Given a simple connected unweighted undirected graph G = (V (G), E(G)) with |V (G)| = n and |E(G)| = m, we present a new algorithm for the all-pairs shortest-path (APSP) problem. The running time of our algorithm is in O(n2 log n). This bound is an improvement over previous best known O(n2.376) time bound of Raimund Seidel (1995) for general graphs. The algorithm presented does not rely on fast matrix multiplication. Our algorithm with slight modifications, enables us to compute the APSP problem for unweighted directed graph in time O(n2 log n), improving a previous best known O(n2.575) time bound of Uri Zwick (2002).
Abstract: Long number multiplications (n ≥ 128-bit) are a
primitive in most cryptosystems. They can be performed better by
using Karatsuba-Ofman technique. This algorithm is easy to
parallelize on workstation network and on distributed memory, and
it-s known as the practical method of choice. Multiplying long
numbers using Karatsuba-Ofman algorithm is fast but is highly
recursive. In this paper, we propose different designs of
implementing Karatsuba-Ofman multiplier. A mixture of sequential
and combinational system design techniques involving pipelining is
applied to our proposed designs. Multiplying large numbers can be
adapted flexibly to time, area and power criteria. Computationally
and occupation constrained in embedded systems such as: smart
cards, mobile phones..., multiplication of finite field elements can be
achieved more efficiently. The proposed designs are compared to
other existing techniques. Mathematical models (Area (n), Delay (n))
of our proposed designs are also elaborated and evaluated on
different FPGAs devices.
Abstract: For higher order multiplications, a huge number of
adders or compressors are to be used to perform the partial product
addition. We have reduced the number of adders by introducing
special kind of adders that are capable to add five/six/seven bits per
decade. These adders are called compressors. Binary counter
property has been merged with the compressor property to develop
high order compressors. Uses of these compressors permit the
reduction of the vertical critical paths. A 16×16 bit multiplier has
been developed using these compressors. These compressors make
the multipliers faster as compared to the conventional design that
have been used 4-2 compressors and 3-2 compressors.
Abstract: In this paper, the hardware implementation of the
RSA public-key cryptographic algorithm is presented. The RSA
cryptographic algorithm is depends on the computation of repeated
modular exponentials.
The Montgomery algorithm is used and modified to reduce
hardware resources and to achieve reasonable operating speed for
FPGA. An efficient architecture for modular multiplications based on
the array multiplier is proposed. We have implemented a RSA
cryptosystem based on Montgomery algorithm. As a result, it is
shown that proposed architecture contributes to small area and
reasonable speed.
Abstract: In this paper, RSA encryption algorithm and its hardware
implementation in Xilinx-s Virtex Field Programmable Gate
Arrays (FPGA) is analyzed. The issues of scalability, flexible performance,
and silicon efficiency for the hardware acceleration of
public key crypto systems are being explored in the present work.
Using techniques based on the interleaved math for exponentiation,
the proposed RSA calculation architecture is compared to existing
FPGA-based solutions for speed, FPGA utilization, and scalability.
The paper covers the RSA encryption algorithm, interleaved multiplication,
Miller Rabin algorithm for primality test, extended Euclidean
math, basic FPGA technology, and the implementation details of
the proposed RSA calculation architecture. Performance of several
alternative hardware architectures is discussed and compared. Finally,
conclusion is drawn, highlighting the advantages of a fully flexible
& parameterized design.
Abstract: Double heterogeneity of randomly located pebbles in
the core and Coated Fuel Particles (CFPs) in the pebbles are specific
features in pebble bed reactors and usually, because of difficulty to
model with MCNP code capabilities, are neglected. In this study,
characteristics of HTR-10, Tsinghua University research reactor, are
used and not only double heterogeneous but also truncated CFPs and
Pebbles are considered.Firstly, 8335 CFPs are distributed randomly
in a pebble and then the core of reactor is filled with those pebbles
and graphite pebbles as moderator such that 57:43 ratio of fuel and
moderator pebbles is established.Finally, four different core
configurations are modeled. They are Simple Cubic (SC) structure
with truncated pebbles,SC structure without truncated pebble, and
Simple Hexagonal(SH) structure without truncated pebbles and SH
structure with truncated pebbles. Results like effective multiplication
factor (Keff), critical height,etc. are compared with available data.
Abstract: The advent of multi-million gate Field Programmable
Gate Arrays (FPGAs) with hardware support for multiplication opens
an opportunity to recreate a significant portion of the front end of a
human cochlea using this technology. In this paper we describe the
implementation of the cochlear filter and show that it is entirely
suited to a single device XC3S500 FPGA implementation .The filter
gave a good fit to real time data with efficiency of hardware usage.
Abstract: In the present work we model a Multiquantum Well
structure Separate Absorption and Charge Multiplication Avalanche
Photodiode (MQW-SACM-APD), while the Absorption region
coincide with the MQW. We consider the nonuniformity of electric
field using split-step method in active region. This model is based on
the carrier rate equations in the different regions of the device. Using
the model we obtain the photocurrent, and dark current. As an
example, InGaAs/InP SACM-APD and MQW-SACM-APD are
simulated. There is a good agreement between the simulation and
experimental results.
Abstract: Over the past years, the EMCCD has had a profound
influence on photon starved imaging applications relying on its unique
multiplication register based on the impact ionization effect in the
silicon. High signal-to-noise ratio (SNR) means high image quality.
Thus, SNR improvement is important for the EMCCD. This work
analyzes the SNR performance of an EMCCD with gain off and on. In
each mode, simplified SNR models are established for different
integration times. The SNR curves are divided into readout noise (or
CIC) region and shot noise region by integration time. Theoretical
SNR values comparing long frame integration and frame adding in
each region are presented and discussed to figure out which method is
more effective. In order to further improve the SNR performance,
pixel binning is introduced into the EMCCD. The results show that
pixel binning does obviously improve the SNR performance, but at the
expensive of the spatial resolution.
Abstract: A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.
Abstract: Encryption and decryption in RSA are done by modular exponentiation which is achieved by repeated modular multiplication. Hence efficiency of modular multiplication directly determines the efficiency of RSA cryptosystem. This paper designs a Modified Montgomery Modular Multiplication in which addition of operands is computed by 4:2 compressor. The basic logic operations in addition are partitioned over two iterations such that parallel computations are performed. This reduces the critical path delay of proposed Montgomery design. The proposed design and RSA are implemented on Virtex 2 and Virtex 5 FPGAs. The two factors partitioning and parallelism have improved the frequency and throughput of proposed design.
Abstract: In this paper is investigated a possible
optimization of some linear algebra problems which can be
solved by parallel processing using the special arrays called
systolic arrays. In this paper are used some special types of
transformations for the designing of these arrays. We show
the characteristics of these arrays. The main focus is on
discussing the advantages of these arrays in parallel
computation of matrix product, with special approach to the
designing of systolic array for matrix multiplication.
Multiplication of large matrices requires a lot of
computational time and its complexity is O(n3 ). There are
developed many algorithms (both sequential and parallel) with
the purpose of minimizing the time of calculations. Systolic
arrays are good suited for this purpose. In this paper we show
that using an appropriate transformation implicates in finding
more optimal arrays for doing the calculations of this type.