Abstract: Digital signal processor, image signal processor and FIR filters have multipliers as an important part of their design. On the basis of Vedic mathematics, Vedic multipliers have come out to be very fast multipliers. One of the image processing applications is edge detection. This research presents a small area and high speed 8 bit Vedic multiplier system comprising of compressor based adders. This results in faster edge detection. This architecture is tested on Xilinx vertex 4 FPGA board and simulations were carried out using the Xilinx synthesis tool. Comparisons are made and this system is found to be smaller in area with high speed (the lesser propagation delay). This compressor based Vedic multiplier is 1.1 times speedier than a typical Vedic multiplier. Also, this Vedic Multiplier is 2 times speedier than a ‘simple’ multiplier.
Abstract: Unmanned Aircraft Systems (UAS) become
indispensable parts of modern airpower as force multiplier. One of
the main advantages of UAS is long endurance. UAS have to take
extra payloads to accomplish different missions but these payloads
decrease endurance of aircraft because of increasing drag. There are
continuing researches to increase the capability of UAS. There are
some vertical thermal air currents, which can cause climb and
increase endurance, in nature. Birds and gliders use thermals to gain
altitude with no effort. UAS have wide wings which can use
thermals like birds and gliders. Thermal regions, which is area of
2000-3000 meter (1 NM), exist all around the world. It is natural and
infinite source. This study analyses if thermal regions can be adopted
and implemented as an assistant tool for UAS route planning. First
and second part of study will contain information about the thermal
regions and current applications about UAS in aviation and climbing
performance with a real example. Continuing parts will analyze the
contribution of thermal regions to UAS endurance. Contribution is
important because planning declaration of UAS navigation rules will
be in 2015.
Abstract: A silicon photomultiplier (SiPM) was designed, fabricated and characterized. The SiPM was based on SACM (Separation of Absorption, Charge and Multiplication) structure, which was optimized for blue light detection in application of positron emission tomography (PET). The achieved SiPM array has a high geometric fill factor of 64% and a low breakdown voltage of about 22V, while the temperature dependence of breakdown voltage is only 17mV/°C. The gain and photon detection efficiency of the device achieved were also measured under illumination of light at 405nm and 460nm wavelengths. The gain of the device is in the order of 106. The photon detection efficiency up to 60% has been observed under 1.8V overvoltage.
Abstract: In this paper a new fast simplification method is
presented. Such method realizes Karnough map with large
number of variables. In order to accelerate the operation of the
proposed method, a new approach for fast detection of group
of ones is presented. Such approach implemented in the
frequency domain. The search operation relies on performing
cross correlation in the frequency domain rather than time one.
It is proved mathematically and practically that the number of
computation steps required for the presented method is less
than that needed by conventional cross correlation. Simulation
results using MATLAB confirm the theoretical computations.
Furthermore, a powerful solution for realization of complex
functions is given. The simplified functions are implemented
by using a new desigen for neural networks. Neural networks
are used because they are fault tolerance and as a result they
can recognize signals even with noise or distortion. This is
very useful for logic functions used in data and computer
communications. Moreover, the implemented functions are
realized with minimum amount of components. This is done
by using modular neural nets (MNNs) that divide the input
space into several homogenous regions. Such approach is
applied to implement XOR function, 16 logic functions on one
bit level, and 2-bit digital multiplier. Compared to previous
non- modular designs, a clear reduction in the order of
computations and hardware requirements is achieved.
Abstract: In this paper a new fast simplification method is presented. Such method realizes Karnough map with large number of variables. In order to accelerate the operation of the proposed method, a new approach for fast detection of group of ones is presented. Such approach implemented in the frequency domain. The search operation relies on performing cross correlation in the frequency domain rather than time one. It is proved mathematically and practically that the number of computation steps required for the presented method is less than that needed by conventional cross correlation. Simulation results using MATLAB confirm the theoretical computations. Furthermore, a powerful solution for realization of complex functions is given. The simplified functions are implemented by using a new desigen for neural networks. Neural networks are used because they are fault tolerance and as a result they can recognize signals even with noise or distortion. This is very useful for logic functions used in data and computer communications. Moreover, the implemented functions are realized with minimum amount of components. This is done by using modular neural nets (MNNs) that divide the input space into several homogenous regions. Such approach is applied to implement XOR function, 16 logic functions on one bit level, and 2-bit digital multiplier. Compared to previous non- modular designs, a clear reduction in the order of computations and hardware requirements is achieved.
Abstract: Long number multiplications (n ≥ 128-bit) are a
primitive in most cryptosystems. They can be performed better by
using Karatsuba-Ofman technique. This algorithm is easy to
parallelize on workstation network and on distributed memory, and
it-s known as the practical method of choice. Multiplying long
numbers using Karatsuba-Ofman algorithm is fast but is highly
recursive. In this paper, we propose different designs of
implementing Karatsuba-Ofman multiplier. A mixture of sequential
and combinational system design techniques involving pipelining is
applied to our proposed designs. Multiplying large numbers can be
adapted flexibly to time, area and power criteria. Computationally
and occupation constrained in embedded systems such as: smart
cards, mobile phones..., multiplication of finite field elements can be
achieved more efficiently. The proposed designs are compared to
other existing techniques. Mathematical models (Area (n), Delay (n))
of our proposed designs are also elaborated and evaluated on
different FPGAs devices.
Abstract: The advent of multi-million gate Field Programmable
Gate Arrays (FPGAs) with hardware support for multiplication opens
an opportunity to recreate a significant portion of the front end of a
human cochlea using this technology. In this paper we describe the
implementation of the cochlear filter and show that it is entirely
suited to a single device XC3S500 FPGA implementation .The filter
gave a good fit to real time data with efficiency of hardware usage.
Abstract: In this paper, a double balanced radio frequency multiplier
is presented which is customized for transmitted reference
ultra wideband (UWB) receivers. The multiplier uses 90nm model
parameters and exploits compensating transistors to provide controllable
gain for a Gilbert core. After performing periodic and quasiperiodic
non linear analyses the RF mixer (multiplier) achieves a
voltage conversion gain of 16 dB and a DSB noise figure of 8.253
dB with very low power consumption. A high degree of LO to RF
isolation (in the range of -94dB), RF to IF isolation (in the range of
-95dB) and LO to IF isolation (in the range of -143dB) is expected
for this design with an input-referred IP3 point of -1.93 dBm and an
input referred 1 dB compression point of -10.67dBm. The amount of
noise at the output is 7.7 nV/√Hz when the LO input is driven by
a 10dBm signal. The mixer manifests better results when compared
with other reported multiplier circuits and its Zero-IF performance
ensures its applicability as TR-UWB multipliers.
Abstract: A systematic way to derive the conserved quantities for the axisymmetric liquid jet, free jet and wall jet using conservation laws is presented. The flow in axisymmetric jets is governed by Prandtl-s momentum boundary layer equation and the continuity equation. The multiplier approach is used to construct a basis of conserved vectors for the system of two partial differential equations for the two velocity components. The basis consists of two conserved vectors. By integrating the corresponding conservation laws across the jet and imposing the boundary conditions, conserved quantities are derived for the axisymmetric liquid and free jet. The multiplier approach applied to the third-order partial differential equation for the stream function yields two local conserved vectors one of which is a non-local conserved vector for the system. One of the conserved vectors gives the conserved quantity for the axisymmetric free jet but the conserved quantity for the wall jet is not obtained from the second conserved vector. The conserved quantity for the axisymmetric wall jet is derived from a non-local conserved vector of the third-order partial differential equation for the stream function. This non-local conserved vector for the third-order partial differential equation for the stream function is obtained by using the stream function as multiplier.
Abstract: A reduced-bit multiplication algorithm based on the ancient Vedic multiplication formulae is proposed in this paper. Both the Vedic multiplication formulae, Urdhva tiryakbhyam and Nikhilam, are first discussed in detail. Urdhva tiryakbhyam, being a general multiplication formula, is equally applicable to all cases of multiplication. It is applied to the digital arithmetic and is shown to yield a multiplier architecture which is very similar to the popular array multiplier. Due to its structure, it leads to a high carry propagation delay in case of multiplication of large numbers. Nikhilam Sutra, on the other hand, is more efficient in the multiplication of large numbers as it reduces the multiplication of two large numbers to that of two smaller numbers. The framework of the proposed algorithm is taken from this Sutra and is further optimized by use of some general arithmetic operations such as expansion and bit-shifting to take advantage of bit-reduction in multiplication. We illustrate the proposed algorithm by reducing a general 4x4-bit multiplication to a single 2 x 2-bit multiplication operation.
Abstract: A new and highly efficient architecture for elliptic curve scalar point multiplication which is optimized for a binary field recommended by NIST and is well-suited for elliptic curve cryptographic (ECC) applications is presented. To achieve the maximum architectural and timing improvements we have reorganized and reordered the critical path of the Lopez-Dahab scalar point multiplication architecture such that logic structures are implemented in parallel and operations in the critical path are diverted to noncritical paths. With G=41, the proposed design is capable of performing a field multiplication over the extension field with degree 163 in 11.92 s with the maximum achievable frequency of 251 MHz on Xilinx Virtex-4 (XC4VLX200) while 22% of the chip area is occupied, where G is the digit size of the underlying digit-serial finite field multiplier.