International Journal of Electrical, Electronic and Communication Sciences

Floating-Point Scaling for BSS Gain Control

Year: 2010 Volume: 4 Issue: 1 206 - 210 Pages

Abstract: In Blind Source Separation (BSS) processing, taking advantage of scaling factor indetermination and based on the floatingpoint representation, we propose a scaling technique applied to the separation matrix, to avoid the saturation or the weakness in the recovered source signals. This technique performs an Automatic Gain Control (AGC) in an on-line BSS environment. We demonstrate the effectiveness of this technique by using the implementation of a division free BSS algorithm with two input, two output. This technique is computationally cheaper and efficient for a hardware implementation.

An Image Encryption Method with Magnitude and Phase Manipulation using Carrier Images

Year: 2008 Volume: 2 Issue: 2 320 - 325 Pages

Abstract: We describe an effective method for image encryption which employs magnitude and phase manipulation using carrier images. Although it involves traditional methods like magnitude and phase encryptions, the novelty of this work lies in deploying the concept of carrier images for encryption purpose. To this end, a carrier image is randomly chosen from a set of stored images. One dimensional (1-D) discrete Fourier transform (DFT) is then carried out on the original image to be encrypted along with the carrier image. Row wise spectral addition and scaling is performed between the magnitude spectra of the original and carrier images by randomly selecting the rows. Similarly, row wise phase addition and scaling is performed between the original and carrier images phase spectra by randomly selecting the rows. The encrypted image obtained by these two operations is further subjected to one more level of magnitude and phase manipulation using another randomly chosen carrier image by 1-D DFT along the columns. The resulting encrypted image is found to be fully distorted, resulting in increasing the robustness of the proposed work. Further, applying the reverse process at the receiver, the decrypted image is found to be distortionless.

Potential of Solar Energy in Zarqa Region

Year: 2011 Volume: 5 Issue: 4 574 - 578 Pages

Abstract: The purpose of this work is to present the potential of solar energy in Zarqa region. The solar radiation along year 2009 was obtained from Pyranometer which measures the global radiation over horizontal surfaces. Solar data in several different forms, over period of 5 minutes, hour-by-hour, daily and monthly data radiation have been presented. Briefly, the yearly global solar radiation in Zarqa is 7297.5 MJ/m2 (2027 kWh/m²) and the average annual solar radiation per day is 20 MJ/m2 (5.5 Kwh/m2). More specifically, the average annual solar radiation per day is 12.9 MJ/m2 (3.57 Kwh/m2) in winter and 25 MJ/m2 (7 Kwh/m2) in summer.

A New Nonlinear Excitation Controller for Transient Stability Enhancement in Power Systems

Year: 2007 Volume: 1 Issue: 8 1180 - 1185 Pages

Abstract: The very nonlinear nature of the generator and system behaviour following a severe disturbance precludes the use of classical linear control technique. In this paper, a new approach of nonlinear control is proposed for transient and steady state stability analysis of a synchronous generator. The control law of the generator excitation is derived from the basis of Lyapunov stability criterion. The overall stability of the system is shown using Lyapunov technique. The application of the proposed controller to simulated generator excitation control under a large sudden fault and wide range of operating conditions demonstrates that the new control strategy is superior to conventional automatic voltage regulator (AVR), and show very promising results.

An Innovative Fuzzy Decision Making Based Genetic Algorithm

Year: 2008 Volume: 2 Issue: 7 1543 - 1546 Pages

Abstract: Several researchers have proposed methods about combination of Genetic Algorithm (GA) and Fuzzy Logic (the use of GA to obtain fuzzy rules and application of fuzzy logic in optimization of GA). In this paper, we suggest a new method in which fuzzy decision making is used to improve the performance of genetic algorithm. In the suggested method, we determine the alleles that enhance the fitness of chromosomes and try to insert them to the next generation. In this algorithm we try to present an innovative vaccination in the process of reproduction in genetic algorithm, with considering the trade off between exploration and exploitation.

Three-Phase High Frequency AC Conversion Circuit with Dual Mode PWM/PDM Control Strategy for High Power IH Applications

Year: 2008 Volume: 2 Issue: 9 2072 - 2078 Pages

Authors:
Nabil A. Ahmed

Abstract: This paper presents a novel three-phase utility frequency to high frequency soft switching power conversion circuit with dual mode pulse width modulation and pulse density modulation for high power induction heating applications as melting of steel and non ferrous metals, annealing of metals, surface hardening of steel and cast iron work pieces and hot water producers, steamers and super heated steamers. This high frequency power conversion circuit can operate from three-phase systems to produce high current for high power induction heating applications under the principles of ZVS and it can regulate its ac output power from the rated value to a low power level. A dual mode modulation control scheme based on high frequency PWM in synchronization with the utility frequency positive and negative half cycles for the proposed high frequency conversion circuit and utility frequency pulse density modulation is produced to extend its soft switching operating range for wide ac output power regulation. A dual packs heat exchanger assembly is designed to be used in consumer and industrial fluid pipeline systems and it is proved to be suitable for the hot water, steam and super heated steam producers. Experiment and simulation results are given in this paper to verify the operation principles of the proposed ac conversion circuit and to evaluate its power regulation and conversion efficiency. Also, the paper presents a mutual coupling model of the induction heating load instead of equivalent transformer circuit model.

Hybrid MAC Protocols Characteristics in Multi-hops Wireless Sensor Networks

Year: 2008 Volume: 2 Issue: 9 2063 - 2071 Pages

Abstract: In the current decade, wireless sensor networks are emerging as a peculiar multi-disciplinary research area. By this way, energy efficiency is one of the fundamental research themes in the design of Medium Access Control (MAC) protocols for wireless sensor networks. Thus, in order to optimize the energy consumption in these networks, a variety of MAC protocols are available in the literature. These schemes were commonly evaluated under simple network density and a few results are published on their robustness in realistic network-s size. We, in this paper, provide an analytical study aiming to highlight the energy waste sources in wireless sensor networks. Then, we experiment three energy efficient hybrid CSMA/CA based MAC protocols optimized for wireless sensor networks: Sensor-MAC (SMAC), Time-out MAC (TMAC) and Traffic aware Energy Efficient MAC (TEEM). We investigate these protocols with different network densities in order to discuss the end-to-end performances of these schemes (i.e. in terms of energy efficiency, delay and throughput). Through Network Simulator (NS- 2) implementations, we explore the behaviors of these protocols with respect to the network density. In fact, this study may help the multihops sensor networks designers to design or select the MAC layer which matches better their applications aims.

Design of Non-Blocking and Rearrangeable Modified Banyan Network with Electro-Optic MZI Switching Elements

Year: 2008 Volume: 2 Issue: 7 1537 - 1542 Pages

Abstract: Banyan networks are really attractive for serving as the optical switching architectures due to their unique properties of small depth and absolute signal loss uniformity. The fact has been established that the limitations of blocking nature and the nonavailability of proper connections due to non-rearrangeable property can be easily ruled out using electro-optic MZI switches as basic switching elements. Combination of the horizontal expansion and vertical stacking of optical banyan networks is an appropriate scheme for constructing non-blocking banyan-based optical switching networks. The interconnected banyan switching fabrics (IBSF) have been considered and analyzed to best serve the purpose of optical switching with electro-optic MZI basic elements. The cross/bar state interchange for the switches has been facilitated by appropriate voltage switching or the by the switching of operating wavelength. The paper is dedicated to the modification of the basic switching element being used as well as the architecture of the switching network.

High Speed Bitwise Search for Digital Forensic System

Year: 2007 Volume: 1 Issue: 8 1176 - 1179 Pages

Abstract: The most common forensic activity is searching a hard disk for string of data. Nowadays, investigators and analysts are increasingly experiencing large, even terabyte sized data sets when conducting digital investigations. Therefore consecutive searching can take weeks to complete successfully. There are two primary search methods: index-based search and bitwise search. Index-based searching is very fast after the initial indexing but initial indexing takes a long time. In this paper, we discuss a high speed bitwise search model for large-scale digital forensic investigations. We used pattern matching board, which is generally used for network security, to search for string and complex regular expressions. Our results indicate that in many cases, the use of pattern matching board can substantially increase the performance of digital forensic search tools.

MinRoot and CMesh: Interconnection Architectures for Network-on-Chip Systems

Year: 2009 Volume: 3 Issue: 6 1392 - 1397 Pages

Abstract: The success of an electronic system in a System-on- Chip is highly dependent on the efficiency of its interconnection network, which is constructed from routers and channels (the routers move data across the channels between nodes). Since neither classical bus based nor point to point architectures can provide scalable solutions and satisfy the tight power and performance requirements of future applications, the Network-on-Chip (NoC) approach has recently been proposed as a promising solution. Indeed, in contrast to the traditional solutions, the NoC approach can provide large bandwidth with moderate area overhead. The selected topology of the components interconnects plays prime rule in the performance of NoC architecture as well as routing and switching techniques that can be used. In this paper, we present two generic NoC architectures that can be customized to the specific communication needs of an application in order to reduce the area with minimal degradation of the latency of the system. An experimental study is performed to compare these structures with basic NoC topologies represented by 2D mesh, Butterfly-Fat Tree (BFT) and SPIN. It is shown that Cluster mesh (CMesh) and MinRoot schemes achieves significant improvements in network latency and energy consumption with only negligible area overhead and complexity over existing architectures. In fact, in the case of basic NoC topologies, CMesh and MinRoot schemes provides substantial savings in area as well, because they requires fewer routers. The simulation results show that CMesh and MinRoot networks outperforms MESH, BFT and SPIN in main performance metrics.

Optimization of a Three-Term Backpropagation Algorithm Used for Neural Network Learning

Year: 2007 Volume: 1 Issue: 12 1934 - 1939 Pages

Authors:
Yahya H. Zweiri

Abstract: The back-propagation algorithm calculates the weight changes of an artificial neural network, and a two-term algorithm with a dynamically optimal learning rate and a momentum factor is commonly used. Recently the addition of an extra term, called a proportional factor (PF), to the two-term BP algorithm was proposed. The third term increases the speed of the BP algorithm. However, the PF term also reduces the convergence of the BP algorithm, and optimization approaches for evaluating the learning parameters are required to facilitate the application of the three terms BP algorithm. This paper considers the optimization of the new back-propagation algorithm by using derivative information. A family of approaches exploiting the derivatives with respect to the learning rate, momentum factor and proportional factor is presented. These autonomously compute the derivatives in the weight space, by using information gathered from the forward and backward procedures. The three-term BP algorithm and the optimization approaches are evaluated using the benchmark XOR problem.

The Performance of an 802.11g/Wi-Fi Network Whilst Streaming Voice Content

Year: 2012 Volume: 6 Issue: 9 1055 - 1061 Pages

Abstract: A simple network model is developed in OPNET to study the performance of the Wi-Fi protocol. The model is simulated in OPNET and performance factors such as load, throughput and delay are analysed from the model. Four applications such as oracle, http, ftp and voice are applied over the Wireless LAN network to determine the throughput. The voice application utilises a considerable amount of bandwidth of up to 5Mbps, as a result the 802.11g standard of the Wi-Fi protocol was chosen which can support a data rate of up to 54Mbps. Results indicate that when the load in the Wi-Fi network is increased the queuing delay on the point-to-point links in the Wi-Fi network significantly reduces until it is comparable to that of WiMAX. In conclusion, the queuing delay of the Wi-Fi protocol for the network model simulated was about 0.00001secs comparable to WiMAX network values.

Efficient Hardware Architecture of the Direct 2- D Transform for the HEVC Standard

Year: 2013 Volume: 7 Issue: 6 770 - 774 Pages

Abstract: This paper presents the hardware design of a unified architecture to compute the 4x4, 8x8 and 16x16 efficient twodimensional (2-D) transform for the HEVC standard. This architecture is based on fast integer transform algorithms. It is designed only with adders and shifts in order to reduce the hardware cost significantly. The goal is to ensure the maximum circuit reuse during the computing while saving 40% for the number of operations. The architecture is developed using FIFOs to compute the second dimension. The proposed hardware was implemented in VHDL. The VHDL RTL code works at 240 MHZ in an Altera Stratix III FPGA. The number of cycles in this architecture varies from 33 in 4-point- 2D-DCT to 172 when the 16-point-2D-DCT is computed. Results show frequency improvements reaching 96% when compared to an architecture described as the direct transcription of the algorithm.

DHCP Message Authentication with an Effective Key Management

Year: 2007 Volume: 1 Issue: 8 1172 - 1175 Pages

Abstract: In this paper we describes the authentication for DHCP (Dynamic Host Configuration Protocol) message which provides the efficient key management and reduces the danger replay attack without an additional packet for a replay attack. And the authentication for DHCP message supports mutual authentication and provides both entity authentication and message authentication. We applied the authentication for DHCP message to the home network environments and tested through a home gateway.

Design of Gain Scheduled Fuzzy PID Controller

Year: 2007 Volume: 1 Issue: 1 91 - 95 Pages

Abstract: An adaptive fuzzy PID controller with gain scheduling is proposed in this paper. The structure of the proposed gain scheduled fuzzy PID (GS_FPID) controller consists of both fuzzy PI-like controller and fuzzy PD-like controller. Both of fuzzy PI-like and PD-like controllers are weighted through adaptive gain scheduling, which are also determined by fuzzy logic inference. A modified genetic algorithm called accumulated genetic algorithm is designed to learn the parameters of fuzzy inference system. In order to learn the number of fuzzy rules required for the TSK model, the fuzzy rules are learned in an accumulated way. In other words, the parameters learned in the previous rules are accumulated and updated along with the parameters in the current rule. It will be shown that the proposed GS_FPID controllers learned by the accumulated GA perform well for not only the regular linear systems but also the higher order and time-delayed systems.

Efficient Pipelined Hardware Implementation of RIPEMD-160 Hash Function

Year: 2008 Volume: 2 Issue: 2 316 - 319 Pages

Abstract: In this paper an efficient implementation of Ripemd- 160 hash function is presented. Hash functions are a special family of cryptographic algorithms, which is used in technological applications with requirements for security, confidentiality and validity. Applications like PKI, IPSec, DSA, MAC-s incorporate hash functions and are used widely today. The Ripemd-160 is emanated from the necessity for existence of very strong algorithms in cryptanalysis. The proposed hardware implementation can be synthesized easily for a variety of FPGA and ASIC technologies. Simulation results, using commercial tools, verified the efficiency of the implementation in terms of performance and throughput. Special care has been taken so that the proposed implementation doesn-t introduce extra design complexity; while in parallel functionality was kept to the required levels.

On the Analysis of Bandwidth Management for Hybrid Load Balancing Scheme in WLANs

Year: 2009 Volume: 3 Issue: 6 1387 - 1391 Pages

Abstract: In wireless networks, bandwidth is scare resource and it is essential to utilize it effectively. This paper analyses effects of using different bandwidth management techniques on the network performances of the Wireless Local Area Networks (WLANs) that use hybrid load balancing scheme. In particular, we study three bandwidth management schemes, namely Complete Sharing (CS), Complete Partitioning (CP), and Partial Sharing (PS). Performances of these schemes are evaluated by simulation experiments in term of percentage of network association blocking. Our results show that the CS scheme can provide relatively low blocking percentage in various network traffic scenarios whereas the PS scheme can enhance quality of services of the multimedia traffic with rather small expenses on the blocking percentage of the best effort traffic.

New Feed-Forward/Feedback Generalized Minimum Variance Self-tuning Pole-placement Controller

Year: 2009 Volume: 3 Issue: 1 129 - 132 Pages

Abstract: A new Feed-Forward/Feedback Generalized Minimum Variance Pole-placement Controller to incorporate the robustness of classical pole-placement into the flexibility of generalized minimum variance self-tuning controller for Single-Input Single-Output (SISO) has been proposed in this paper. The design, which provides the user with an adaptive mechanism, which ensures that the closed loop poles are, located at their pre-specified positions. In addition, the controller design which has a feed-forward/feedback structure overcomes the certain limitations existing in similar poleplacement control designs whilst retaining the simplicity of adaptation mechanisms used in other designs. It tracks set-point changes with the desired speed of response, penalizes excessive control action, and can be applied to non-minimum phase systems. Besides, at steady state, the controller has the ability to regulate the constant load disturbance to zero. Example simulation results using both simulated and real plant models demonstrate the effectiveness of the proposed controller.

Keywords:
Pole-placement
Minimum variance control
self-tuning control and feedforward control.

Gate Tunnel Current Calculation for NMOSFET Based on Deep Sub-Micron Effects

Year: 2009 Volume: 3 Issue: 3 556 - 564 Pages

Abstract: Aggressive scaling of MOS devices requires use of ultra-thin gate oxides to maintain a reasonable short channel effect and to take the advantage of higher density, high speed, lower cost etc. Such thin oxides give rise to high electric fields, resulting in considerable gate tunneling current through gate oxide in nano regime. Consequently, accurate analysis of gate tunneling current is very important especially in context of low power application. In this paper, a simple and efficient analytical model has been developed for channel and source/drain overlap region gate tunneling current through ultra thin gate oxide n-channel MOSFET with inevitable deep submicron effect (DSME).The results obtained have been verified with simulated and reported experimental results for the purpose of validation. It is shown that the calculated tunnel current is well fitted to the measured one over the entire oxide thickness range. The proposed model is suitable enough to be used in circuit simulator due to its simplicity. It is observed that neglecting deep sub-micron effect may lead to large error in the calculated gate tunneling current. It is found that temperature has almost negligible effect on gate tunneling current. It is also reported that gate tunneling current reduces with the increase of gate oxide thickness. The impact of source/drain overlap length is also assessed on gate tunneling current.

Evaluation of Power Factor Corrected AC - DC Converters and Controllers to meet UPS Performance Index

Year: 2009 Volume: 3 Issue: 4 1033 - 1041 Pages

Abstract: Harmonic pollution and low power factor in power systems caused by power converters have been of great concern. To overcome these problems several converter topologies using advanced semiconductor devices and control schemes have been proposed. This investigation is to identify a low cost, small size, efficient and reliable ac to dc converter to meet the input performance index of UPS. The performance of single phase and three phase ac to dc converter along with various control techniques are studied and compared. The half bridge converter topology with linear current control is identified as most suitable. It is simple, energy efficient because of single switch power loss and transformer-less operation of UPS. The results are validated practically using a prototype built using IGBT and analog controller. The performance for both single and three-phase system is verified. Digital implementation of closed loop control achieves higher reliability. Its cost largely depends on chosen bit precision. The minimal bit precision for optimum converter performance is identified as 16-bit with fixed-point operation. From the investigation and practical implementation it is concluded that half bridge ac – dc converter along with digital linear controller meets the performance index of UPS for single and three phase systems.